tracking down sync failure when stage not dynamically ready

[ieee754fpu.git] / src / add / test_buf_pipe.py

diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 315556355205fdf80a7022ac5a9eff47808165ad..7cdb7ebdedbf467e9296767dbb277bf0dd45df9c 100644 (file)
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -205,6 +205,7 @@ class Test5:
                     send = True
                 else:
                     send = randint(0, send_range) != 0
+                send = True
                 o_p_ready = yield self.dut.p.o_ready
                 if not o_p_ready:
                     yield
@@ -597,6 +598,7 @@ class ExampleStageDelayCls(StageCls):
     @property
     def p_o_ready(self):
         return Const(1)
+        return self.count == 0
 
     @property
     def n_o_valid(self):
@@ -607,6 +609,11 @@ class ExampleStageDelayCls(StageCls):
         """
         return i + 1
 
+    def elaborate(self, platform):
+        m = Module()
+        m.d.sync += self.count.eq(~self.count)
+        return m
+
 
 class ExampleBufDelayedPipe(BufferedPipeline):
     """ an example of how to use the buffered pipeline.
@@ -616,6 +623,11 @@ class ExampleBufDelayedPipe(BufferedPipeline):
         stage = ExampleStageDelayCls()
         BufferedPipeline.__init__(self, stage, stage_ctl=True)
 
+    def elaborate(self, platform):
+        m = BufferedPipeline.elaborate(self, platform)
+        m.submodules.stage = self.stage
+        return m
+
 
 class ExampleBufPipe3(ControlBase):
     """ Example of how to do delayed pipeline, where the stage signals