call ControlBase.elaborate

[ieee754fpu.git] / src / add / test_fsm_experiment.py

diff --git a/src/add/test_fsm_experiment.py b/src/add/test_fsm_experiment.py
index b6b2a9dce85dc231794ceafbf39a6dda274cccb6..782fc61202679eab0a7e78f85788086483d7b674 100644 (file)
--- a/src/add/test_fsm_experiment.py
+++ b/src/add/test_fsm_experiment.py
@@ -93,7 +93,7 @@ class FPDIVPipe(ControlBase):
         return self.fpdiv.out_z.v # return z output
 
     def elaborate(self, platform):
-        self.m = m = ControlBase._elaborate(self, platform)
+        self.m = m = ControlBase.elaborate(self, platform)
 
         m.submodules.fpdiv = self.fpdiv