pass in flatten/processing function into _connect_in/out

[ieee754fpu.git] / src / add / test_inout_mux_pipe.py

diff --git a/src/add/test_inout_mux_pipe.py b/src/add/test_inout_mux_pipe.py
index c30ba644664471000b6783a3bb313ed5dc6520f4..92b6f53f3b724ca73567b63c8ec9952cae97494c 100644 (file)
--- a/src/add/test_inout_mux_pipe.py
+++ b/src/add/test_inout_mux_pipe.py
@@ -11,21 +11,9 @@ from nmigen import Module, Signal, Cat, Value
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
-from multipipe import CombMultiOutPipeline
+from multipipe import CombMultiOutPipeline, CombMuxOutPipe
 from multipipe import PriorityCombMuxInPipe
-from singlepipe import UnbufferedPipeline
-
-
-class MuxCombPipeline(CombMultiOutPipeline):
-    def __init__(self, stage, n_len):
-        # HACK: stage is also the n-way multiplexer
-        CombMultiOutPipeline.__init__(self, stage, n_len=n_len, n_mux=stage)
-
-        # HACK: n-mux is also the stage... so set the muxid equal to input mid
-        stage.m_id = self.p.i_data.mid
-
-    def ports(self):
-        return self.p_mux.ports()
+from singlepipe import SimpleHandshake
 
 
 class PassData: # (Value):
@@ -62,9 +50,9 @@ class PassThroughStage:
 
 
 
-class PassThroughPipe(UnbufferedPipeline):
+class PassThroughPipe(SimpleHandshake):
     def __init__(self):
-        UnbufferedPipeline.__init__(self, PassThroughStage())
+        SimpleHandshake.__init__(self, PassThroughStage())
 
 
 class InputTest:
@@ -156,16 +144,6 @@ class TestPriorityMuxPipe(PriorityCombMuxInPipe):
         stage = PassThroughStage()
         PriorityCombMuxInPipe.__init__(self, stage, p_len=self.num_rows)
 
-    def ports(self):
-        res = []
-        for i in range(len(self.p)):
-            res += [self.p[i].i_valid, self.p[i].o_ready] + \
-                    self.p[i].i_data.ports()
-        res += [self.n.i_ready, self.n.o_valid] + \
-                self.n.o_data.ports()
-        return res
-
-
 
 class OutputTest:
     def __init__(self, dut):
@@ -204,19 +182,11 @@ class OutputTest:
         yield rs.i_valid.eq(0)
 
 
-class TestMuxOutPipe(MuxCombPipeline):
+class TestMuxOutPipe(CombMuxOutPipe):
     def __init__(self, num_rows):
         self.num_rows = num_rows
         stage = PassThroughStage()
-        MuxCombPipeline.__init__(self, stage, n_len=self.num_rows)
-
-    def ports(self):
-        res = [self.p.i_valid, self.p.o_ready] + \
-                self.p.i_data.ports()
-        for i in range(len(self.n)):
-            res += [self.n[i].i_ready, self.n[i].o_valid] + \
-                    self.n[i].o_data.ports()
-        return res
+        CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
 
 
 class TestInOutPipe: