pass in flatten/processing function into _connect_in/out

[ieee754fpu.git] / src / add / test_outmux_pipe.py

diff --git a/src/add/test_outmux_pipe.py b/src/add/test_outmux_pipe.py
index 3e8a5559d17a28a30dd54de187e5a664e06d5e3a..7c25f38498c6b23c58342bdcde251268d855c475 100644 (file)
--- a/src/add/test_outmux_pipe.py
+++ b/src/add/test_outmux_pipe.py
@@ -5,7 +5,7 @@ from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
 from multipipe import CombMuxOutPipe
-from singlepipe import UnbufferedPipeline
+from singlepipe import SimpleHandshake
 
 
 class PassInData:
@@ -43,9 +43,9 @@ class PassThroughDataStage:
 
 
 
-class PassThroughPipe(UnbufferedPipeline):
+class PassThroughPipe(SimpleHandshake):
     def __init__(self):
-        UnbufferedPipeline.__init__(self, PassThroughDataStage())
+        SimpleHandshake.__init__(self, PassThroughDataStage())
 
 
 
@@ -221,15 +221,6 @@ class TestPriorityMuxPipe(CombMuxOutPipe):
         stage = PassThroughStage()
         CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
 
-    def ports(self):
-        res = [self.p.i_valid, self.p.o_ready] + \
-                self.p.i_data.ports()
-        for i in range(len(self.n)):
-            res += [self.n[i].i_ready, self.n[i].o_valid] + \
-                    [self.n[i].o_data]
-                    #self.n[i].o_data.ports()
-        return res
-
 
 class TestSyncToPriorityPipe:
     def __init__(self):