pass in flatten/processing function into _connect_in/out

[ieee754fpu.git] / src / add / test_outmux_pipe.py

diff --git a/src/add/test_outmux_pipe.py b/src/add/test_outmux_pipe.py
index 560ef7387a54332f51f1caf719c56a7b8ca1a8cd..7c25f38498c6b23c58342bdcde251268d855c475 100644 (file)
--- a/src/add/test_outmux_pipe.py
+++ b/src/add/test_outmux_pipe.py
@@ -4,20 +4,8 @@ from nmigen import Module, Signal, Cat
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
-from multipipe import CombMultiOutPipeline
-from singlepipe import UnbufferedPipeline
-
-
-class MuxUnbufferedPipeline(CombMultiOutPipeline):
-    def __init__(self, stage, n_len):
-        # HACK: stage is also the n-way multiplexer
-        CombMultiOutPipeline.__init__(self, stage, n_len=n_len, n_mux=stage)
-
-        # HACK: n-mux is also the stage... so set the muxid equal to input mid
-        stage.m_id = self.p.i_data.mid
-
-    def ports(self):
-        return self.p_mux.ports()
+from multipipe import CombMuxOutPipe
+from singlepipe import SimpleHandshake
 
 
 class PassInData:
@@ -55,9 +43,9 @@ class PassThroughDataStage:
 
 
 
-class PassThroughPipe(UnbufferedPipeline):
+class PassThroughPipe(SimpleHandshake):
     def __init__(self):
-        UnbufferedPipeline.__init__(self, PassThroughDataStage())
+        SimpleHandshake.__init__(self, PassThroughDataStage())
 
 
 
@@ -227,20 +215,11 @@ class OutputTest:
                     yield
 
 
-class TestPriorityMuxPipe(MuxUnbufferedPipeline):
+class TestPriorityMuxPipe(CombMuxOutPipe):
     def __init__(self, num_rows):
         self.num_rows = num_rows
         stage = PassThroughStage()
-        MuxUnbufferedPipeline.__init__(self, stage, n_len=self.num_rows)
-
-    def ports(self):
-        res = [self.p.i_valid, self.p.o_ready] + \
-                self.p.i_data.ports()
-        for i in range(len(self.n)):
-            res += [self.n[i].i_ready, self.n[i].o_valid] + \
-                    [self.n[i].o_data]
-                    #self.n[i].o_data.ports()
-        return res
+        CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
 
 
 class TestSyncToPriorityPipe: