pass in flatten/processing function into _connect_in/out

[ieee754fpu.git] / src / add / test_outmux_pipe.py

diff --git a/src/add/test_outmux_pipe.py b/src/add/test_outmux_pipe.py
index 837a1eb25683d8026a010b3a31f3cb5a2f296243..7c25f38498c6b23c58342bdcde251268d855c475 100644 (file)
--- a/src/add/test_outmux_pipe.py
+++ b/src/add/test_outmux_pipe.py
@@ -4,19 +4,8 @@ from nmigen import Module, Signal, Cat
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
-from multipipe import CombMultiOutPipeline
-
-
-class MuxUnbufferedPipeline(CombMultiOutPipeline):
-    def __init__(self, stage, n_len):
-        # HACK: stage is also the n-way multiplexer
-        CombMultiOutPipeline.__init__(self, stage, n_len=n_len, n_mux=stage)
-
-        # HACK: n-mux is also the stage... so set the muxid equal to input mid
-        stage.m_id = self.p.i_data.mid
-
-    def ports(self):
-        return self.p_mux.ports()
+from multipipe import CombMuxOutPipe
+from singlepipe import SimpleHandshake
 
 
 class PassInData:
@@ -37,12 +26,29 @@ class PassThroughStage:
         return PassInData()
 
     def ospec(self):
-        return Signal(16, reset_less=True)
+        return Signal(16, name="data_out", reset_less=True)
                 
     def process(self, i):
         return i.data
 
 
+class PassThroughDataStage:
+    def ispec(self):
+        return PassInData()
+    def ospec(self):
+        return self.ispec() # same as ospec
+
+    def process(self, i):
+        return i # pass-through
+
+
+
+class PassThroughPipe(SimpleHandshake):
+    def __init__(self):
+        SimpleHandshake.__init__(self, PassThroughDataStage())
+
+
+
 
 def testbench(dut):
     stb = yield dut.out_op.stb
@@ -209,11 +215,28 @@ class OutputTest:
                     yield
 
 
-class TestPriorityMuxPipe(MuxUnbufferedPipeline):
+class TestPriorityMuxPipe(CombMuxOutPipe):
+    def __init__(self, num_rows):
+        self.num_rows = num_rows
+        stage = PassThroughStage()
+        CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
+
+
+class TestSyncToPriorityPipe:
     def __init__(self):
         self.num_rows = 4
-        stage = PassThroughStage()
-        MuxUnbufferedPipeline.__init__(self, stage, n_len=self.num_rows)
+        self.pipe = PassThroughPipe()
+        self.muxpipe = TestPriorityMuxPipe(self.num_rows)
+
+        self.p = self.pipe.p
+        self.n = self.muxpipe.n
+
+    def elaborate(self, platform):
+        m = Module()
+        m.submodules += self.pipe
+        m.submodules += self.muxpipe
+        m.d.comb += self.pipe.n.connect_to_next(self.muxpipe.p)
+        return m
 
     def ports(self):
         res = [self.p.i_valid, self.p.o_ready] + \
@@ -226,7 +249,7 @@ class TestPriorityMuxPipe(MuxUnbufferedPipeline):
 
 
 if __name__ == '__main__':
-    dut = TestPriorityMuxPipe()
+    dut = TestSyncToPriorityPipe()
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_outmux_pipe.il", "w") as f:
         f.write(vl)