experimenting with dual add

[ieee754fpu.git] / src / add / unit_test_single.py

diff --git a/src/add/unit_test_single.py b/src/add/unit_test_single.py
index c6d7861f731e0fd6a0fc597b3a8194d4e2a00875..ca5c14aa14f5365c2b2e0168fcab7a4aace5fffb 100644 (file)
--- a/src/add/unit_test_single.py
+++ b/src/add/unit_test_single.py
@@ -53,16 +53,14 @@ def get_case(dut, a, b):
         out_z_stb = (yield dut.out_z.stb)
         if not out_z_stb:
             continue
+        out_z = yield dut.out_z.v
+        yield dut.out_z.ack.eq(0)
         yield dut.in_a.stb.eq(0)
         yield dut.in_b.stb.eq(0)
-        yield dut.out_z.ack.eq(1)
-        yield
-        yield dut.out_z.ack.eq(0)
-        yield
         yield
+        yield dut.out_z.ack.eq(1)
         break
 
-    out_z = yield dut.out_z.v
     return out_z
 
 def check_case(dut, a, b, z):