finished __mergable_check

[bigint-presentation-code.git] / src / bigint_presentation_code / _tests / test_compiler_ir.py

diff --git a/src/bigint_presentation_code/_tests/test_compiler_ir.py b/src/bigint_presentation_code/_tests/test_compiler_ir.py
index 60d8b445a4c64857ab305518599f2a0c0ed7114c..75e8349b79e7c8c0a01f72971e32a5dd79c9ca5c 100644 (file)
--- a/src/bigint_presentation_code/_tests/test_compiler_ir.py
+++ b/src/bigint_presentation_code/_tests/test_compiler_ir.py
@@ -196,6 +196,54 @@ class TestCompilerIR(unittest.TestCase):
         self.assertEqual(
             repr(fn_analysis.all_program_points),
             "<range:ops[0]:Early..ops[7]:Early>")
+        self.assertEqual(repr(fn_analysis.copies), "FMap({})")
+        self.assertEqual(
+            repr(fn_analysis.const_ssa_vals),
+            "FMap({"
+            "<vl.outputs[0]: <VL_MAXVL>>: (32,), "
+            "<li.outputs[0]: <I64*32>>: ("
+            "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, "
+            "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), "
+            "<ca.outputs[0]: <CA>>: (1,)})"
+        )
+        self.assertEqual(
+            repr(fn_analysis.const_ssa_val_sub_regs),
+            "FMap({"
+            "<vl.outputs[0]: <VL_MAXVL>>[0]: 32, "
+            "<li.outputs[0]: <I64*32>>[0]: 0, "
+            "<li.outputs[0]: <I64*32>>[1]: 0, "
+            "<li.outputs[0]: <I64*32>>[2]: 0, "
+            "<li.outputs[0]: <I64*32>>[3]: 0, "
+            "<li.outputs[0]: <I64*32>>[4]: 0, "
+            "<li.outputs[0]: <I64*32>>[5]: 0, "
+            "<li.outputs[0]: <I64*32>>[6]: 0, "
+            "<li.outputs[0]: <I64*32>>[7]: 0, "
+            "<li.outputs[0]: <I64*32>>[8]: 0, "
+            "<li.outputs[0]: <I64*32>>[9]: 0, "
+            "<li.outputs[0]: <I64*32>>[10]: 0, "
+            "<li.outputs[0]: <I64*32>>[11]: 0, "
+            "<li.outputs[0]: <I64*32>>[12]: 0, "
+            "<li.outputs[0]: <I64*32>>[13]: 0, "
+            "<li.outputs[0]: <I64*32>>[14]: 0, "
+            "<li.outputs[0]: <I64*32>>[15]: 0, "
+            "<li.outputs[0]: <I64*32>>[16]: 0, "
+            "<li.outputs[0]: <I64*32>>[17]: 0, "
+            "<li.outputs[0]: <I64*32>>[18]: 0, "
+            "<li.outputs[0]: <I64*32>>[19]: 0, "
+            "<li.outputs[0]: <I64*32>>[20]: 0, "
+            "<li.outputs[0]: <I64*32>>[21]: 0, "
+            "<li.outputs[0]: <I64*32>>[22]: 0, "
+            "<li.outputs[0]: <I64*32>>[23]: 0, "
+            "<li.outputs[0]: <I64*32>>[24]: 0, "
+            "<li.outputs[0]: <I64*32>>[25]: 0, "
+            "<li.outputs[0]: <I64*32>>[26]: 0, "
+            "<li.outputs[0]: <I64*32>>[27]: 0, "
+            "<li.outputs[0]: <I64*32>>[28]: 0, "
+            "<li.outputs[0]: <I64*32>>[29]: 0, "
+            "<li.outputs[0]: <I64*32>>[30]: 0, "
+            "<li.outputs[0]: <I64*32>>[31]: 0, "
+            "<ca.outputs[0]: <CA>>[0]: 1})"
+        )
 
     def test_repr(self):
         fn, _arg = self.make_add_fn()
@@ -962,6 +1010,36 @@ class TestCompilerIR(unittest.TestCase):
             "    <spread.outputs[1]: <I64>>, <spread.outputs[0]: <I64>>,\n"
             "    <vl.outputs[0]: <VL_MAXVL>>)"
         )
+        fn_analysis = FnAnalysis(fn)
+        self.assertEqual(
+            repr(fn_analysis.copies),
+            "FMap({"
+            "<spread.outputs[0]: <I64>>[0]: <li.outputs[0]: <I64*4>>[0], "
+            "<spread.outputs[1]: <I64>>[0]: <li.outputs[0]: <I64*4>>[1], "
+            "<spread.outputs[2]: <I64>>[0]: <li.outputs[0]: <I64*4>>[2], "
+            "<spread.outputs[3]: <I64>>[0]: <li.outputs[0]: <I64*4>>[3], "
+            "<concat.outputs[0]: <I64*4>>[0]: <li.outputs[0]: <I64*4>>[3], "
+            "<concat.outputs[0]: <I64*4>>[1]: <li.outputs[0]: <I64*4>>[2], "
+            "<concat.outputs[0]: <I64*4>>[2]: <li.outputs[0]: <I64*4>>[1], "
+            "<concat.outputs[0]: <I64*4>>[3]: <li.outputs[0]: <I64*4>>[0]})"
+        )
+        self.assertEqual(
+            repr(fn_analysis.const_ssa_val_sub_regs),
+            "FMap({"
+            "<vl.outputs[0]: <VL_MAXVL>>[0]: 4, "
+            "<li.outputs[0]: <I64*4>>[0]: 0, "
+            "<li.outputs[0]: <I64*4>>[1]: 0, "
+            "<li.outputs[0]: <I64*4>>[2]: 0, "
+            "<li.outputs[0]: <I64*4>>[3]: 0, "
+            "<spread.outputs[0]: <I64>>[0]: 0, "
+            "<spread.outputs[1]: <I64>>[0]: 0, "
+            "<spread.outputs[2]: <I64>>[0]: 0, "
+            "<spread.outputs[3]: <I64>>[0]: 0, "
+            "<concat.outputs[0]: <I64*4>>[0]: 0, "
+            "<concat.outputs[0]: <I64*4>>[1]: 0, "
+            "<concat.outputs[0]: <I64*4>>[2]: 0, "
+            "<concat.outputs[0]: <I64*4>>[3]: 0})"
+        )
 
 
 if __name__ == "__main__":