add pre_ra_insert_copies

[bigint-presentation-code.git] / src / bigint_presentation_code / _tests / test_compiler_ir2.py

diff --git a/src/bigint_presentation_code/_tests/test_compiler_ir2.py b/src/bigint_presentation_code/_tests/test_compiler_ir2.py
index dfa43e68b24aa7e1bc81a8bc9370300a06ca395e..288aea67b5236cae9f17261a573a4b87815bf989 100644 (file)
--- a/src/bigint_presentation_code/_tests/test_compiler_ir2.py
+++ b/src/bigint_presentation_code/_tests/test_compiler_ir2.py
@@ -66,6 +66,101 @@ class TestCompilerIR(unittest.TestCase):
             "outputs=(), name='st')",
         ])
 
+    def test_pre_ra_insert_copies(self):
+        fn, _arg = self.make_add_fn()
+        fn.pre_ra_insert_copies()
+        self.assertEqual([repr(i) for i in fn.ops], [
+            "Op(kind=OpKind.FuncArgR3, "
+            "inputs=[], "
+            "immediates=[], "
+            "outputs=(<arg#0: <I64>>,), name='arg')",
+            "Op(kind=OpKind.CopyFromReg, "
+            "inputs=[<arg#0: <I64>>], "
+            "immediates=[], "
+            "outputs=(<2#0: <I64>>,), name='2')",
+            "Op(kind=OpKind.SetVLI, "
+            "inputs=[], "
+            "immediates=[32], "
+            "outputs=(<vl#0: <VL_MAXVL>>,), name='vl')",
+            "Op(kind=OpKind.CopyToReg, "
+            "inputs=[<2#0: <I64>>], "
+            "immediates=[], "
+            "outputs=(<3#0: <I64>>,), name='3')",
+            "Op(kind=OpKind.SvLd, "
+            "inputs=[<3#0: <I64>>, <vl#0: <VL_MAXVL>>], "
+            "immediates=[0], "
+            "outputs=(<ld#0: <I64*32>>,), name='ld')",
+            "Op(kind=OpKind.SetVLI, "
+            "inputs=[], "
+            "immediates=[32], "
+            "outputs=(<4#0: <VL_MAXVL>>,), name='4')",
+            "Op(kind=OpKind.VecCopyFromReg, "
+            "inputs=[<ld#0: <I64*32>>, <4#0: <VL_MAXVL>>], "
+            "immediates=[], "
+            "outputs=(<5#0: <I64*32>>,), name='5')",
+            "Op(kind=OpKind.SvLI, "
+            "inputs=[<vl#0: <VL_MAXVL>>], "
+            "immediates=[0], "
+            "outputs=(<li#0: <I64*32>>,), name='li')",
+            "Op(kind=OpKind.SetVLI, "
+            "inputs=[], "
+            "immediates=[32], "
+            "outputs=(<6#0: <VL_MAXVL>>,), name='6')",
+            "Op(kind=OpKind.VecCopyFromReg, "
+            "inputs=[<li#0: <I64*32>>, <6#0: <VL_MAXVL>>], "
+            "immediates=[], "
+            "outputs=(<7#0: <I64*32>>,), name='7')",
+            "Op(kind=OpKind.SetCA, "
+            "inputs=[], "
+            "immediates=[], "
+            "outputs=(<ca#0: <CA>>,), name='ca')",
+            "Op(kind=OpKind.SetVLI, "
+            "inputs=[], "
+            "immediates=[32], "
+            "outputs=(<8#0: <VL_MAXVL>>,), name='8')",
+            "Op(kind=OpKind.VecCopyToReg, "
+            "inputs=[<5#0: <I64*32>>, <8#0: <VL_MAXVL>>], "
+            "immediates=[], "
+            "outputs=(<9#0: <I64*32>>,), name='9')",
+            "Op(kind=OpKind.SetVLI, "
+            "inputs=[], "
+            "immediates=[32], "
+            "outputs=(<10#0: <VL_MAXVL>>,), name='10')",
+            "Op(kind=OpKind.VecCopyToReg, "
+            "inputs=[<7#0: <I64*32>>, <10#0: <VL_MAXVL>>], "
+            "immediates=[], "
+            "outputs=(<11#0: <I64*32>>,), name='11')",
+            "Op(kind=OpKind.SvAddE, "
+            "inputs=[<9#0: <I64*32>>, <11#0: <I64*32>>, <ca#0: <CA>>, "
+            "<vl#0: <VL_MAXVL>>], "
+            "immediates=[], "
+            "outputs=(<add#0: <I64*32>>, <add#1: <CA>>), name='add')",
+            "Op(kind=OpKind.SetVLI, "
+            "inputs=[], "
+            "immediates=[32], "
+            "outputs=(<12#0: <VL_MAXVL>>,), name='12')",
+            "Op(kind=OpKind.VecCopyFromReg, "
+            "inputs=[<add#0: <I64*32>>, <12#0: <VL_MAXVL>>], "
+            "immediates=[], "
+            "outputs=(<13#0: <I64*32>>,), name='13')",
+            "Op(kind=OpKind.SetVLI, "
+            "inputs=[], "
+            "immediates=[32], "
+            "outputs=(<14#0: <VL_MAXVL>>,), name='14')",
+            "Op(kind=OpKind.VecCopyToReg, "
+            "inputs=[<13#0: <I64*32>>, <14#0: <VL_MAXVL>>], "
+            "immediates=[], "
+            "outputs=(<15#0: <I64*32>>,), name='15')",
+            "Op(kind=OpKind.CopyToReg, "
+            "inputs=[<2#0: <I64>>], "
+            "immediates=[], "
+            "outputs=(<16#0: <I64>>,), name='16')",
+            "Op(kind=OpKind.SvStd, "
+            "inputs=[<15#0: <I64*32>>, <16#0: <I64>>, <vl#0: <VL_MAXVL>>], "
+            "immediates=[0], "
+            "outputs=(), name='st')",
+        ])
+
     def test_sim(self):
         fn, arg = self.make_add_fn()
         addr = 0x100