finished __mergable_check

[bigint-presentation-code.git] / src / bigint_presentation_code / compiler_ir.py

diff --git a/src/bigint_presentation_code/compiler_ir.py b/src/bigint_presentation_code/compiler_ir.py
index e3a4ed5bb4fcfc28bbc65c5a687954a8d5fe80df..12a32f1b6ad28bcf2258e804cc0958f1507047a4 100644 (file)
--- a/src/bigint_presentation_code/compiler_ir.py
+++ b/src/bigint_presentation_code/compiler_ir.py
@@ -311,7 +311,7 @@ class ProgramRange(Sequence[ProgramPoint], metaclass=InternedMeta):
         return f"<range:{start}..{stop}>"
 
 
-@plain_data(frozen=True, unsafe_hash=True)
+@plain_data(frozen=True, unsafe_hash=True, repr=False)
 @final
 class SSAValSubReg(metaclass=InternedMeta):
     __slots__ = "ssa_val", "reg_idx"
@@ -323,6 +323,10 @@ class SSAValSubReg(metaclass=InternedMeta):
         self.ssa_val = ssa_val
         self.reg_idx = reg_idx
 
+    def __repr__(self):
+        # type: () -> str
+        return f"{self.ssa_val}[{self.reg_idx}]"
+
 
 @plain_data(frozen=True, eq=False, repr=False)
 @final
@@ -448,7 +452,7 @@ class FnAnalysis:
                 retval[SSAValSubReg(ssa_val, reg_idx)] = v
         return FMap(retval)
 
-    def are_always_equal(self, a, b):
+    def is_always_equal(self, a, b):
         # type: (SSAValSubReg, SSAValSubReg) -> bool
         """check if a and b are known to be always equal to each other.
         This means they can be allocated to the same location if other
@@ -2338,7 +2342,7 @@ class BaseSimState(metaclass=ABCMeta):
 
     @abstractmethod
     def __setitem__(self, ssa_val, value):
-        # type: (SSAVal, tuple[int, ...]) -> None
+        # type: (SSAVal, Iterable[int]) -> None
         ...
 
 
@@ -2387,7 +2391,8 @@ class PreRABaseSimState(BaseSimState):
         raise KeyError("SSAVal has no value set", ssa_val)
 
     def __setitem__(self, ssa_val, value):
-        # type: (SSAVal, tuple[int, ...]) -> None
+        # type: (SSAVal, Iterable[int]) -> None
+        value = tuple(map(int, value))
         if len(value) != ssa_val.ty.reg_len:
             raise ValueError("value has wrong len")
         self.ssa_vals[ssa_val] = value
@@ -2496,7 +2501,8 @@ class PostRASimState(BaseSimState):
         return tuple(retval)
 
     def __setitem__(self, ssa_val, value):
-        # type: (SSAVal, tuple[int, ...]) -> None
+        # type: (SSAVal, Iterable[int]) -> None
+        value = tuple(map(int, value))
         if len(value) != ssa_val.ty.reg_len:
             raise ValueError("value has wrong len")
         loc = self.ssa_val_to_loc_map[ssa_val]