change Op/Ty/SSAVal reprs to be easier to read

[bigint-presentation-code.git] / src / bigint_presentation_code / compiler_ir2.py

diff --git a/src/bigint_presentation_code/compiler_ir2.py b/src/bigint_presentation_code/compiler_ir2.py
index 00e62219c100fa8a26e542f9a72ca8fb1587a850..e6ffe4e606076577b57bb64a208b8b70a42c7954 100644 (file)
--- a/src/bigint_presentation_code/compiler_ir2.py
+++ b/src/bigint_presentation_code/compiler_ir2.py
@@ -88,7 +88,7 @@ class BaseTy(Enum):
         return "BaseTy." + self._name_
 
 
-@plain_data(frozen=True, unsafe_hash=True)
+@plain_data(frozen=True, unsafe_hash=True, repr=False)
 @final
 class Ty:
     __slots__ = "base_ty", "reg_len"
@@ -113,6 +113,14 @@ class Ty:
         self.base_ty = base_ty
         self.reg_len = reg_len
 
+    def __repr__(self):
+        # type: () -> str
+        if self.reg_len != 1:
+            reg_len = f"*{self.reg_len}"
+        else:
+            reg_len = ""
+        return f"<{self.base_ty._name_}{reg_len}>"
+
 
 @unique
 @final
@@ -1030,7 +1038,7 @@ class SSAVal:
 
     def __repr__(self):
         # type: () -> str
-        return f"<{self.op.name}#{self.output_idx}>"
+        return f"<{self.op.name}#{self.output_idx}: {self.ty}>"
 
     @cached_property
     def defining_descriptor(self):
@@ -1181,7 +1189,7 @@ class OpImmediates(OpInputSeq[int, range]):
         super().__init__(items, op)
 
 
-@plain_data(frozen=True, eq=False)
+@plain_data(frozen=True, eq=False, repr=False)
 @final
 class Op:
     __slots__ = "fn", "properties", "inputs", "immediates", "outputs", "name"
@@ -1209,6 +1217,25 @@ class Op:
     def __hash__(self):
         return object.__hash__(self)
 
+    def __repr__(self):
+        # type: () -> str
+        field_vals = []  # type: list[str]
+        for name in fields(self):
+            if name == "properties":
+                name = "kind"
+            elif name == "fn":
+                continue
+            try:
+                value = getattr(self, name)
+            except AttributeError:
+                field_vals.append(f"{name}=<not set>")
+                continue
+            if isinstance(value, OpInputSeq):
+                value = list(value)  # type: ignore
+            field_vals.append(f"{name}={value!r}")
+        field_vals_str = ", ".join(field_vals)
+        return f"Op({field_vals_str})"
+
     def pre_ra_sim(self, state):
         # type: (PreRASimState) -> None
         for inp in self.inputs: