working on generating output assembly

[bigint-presentation-code.git] / src / bigint_presentation_code / test_compiler_ir.py

diff --git a/src/bigint_presentation_code/test_compiler_ir.py b/src/bigint_presentation_code/test_compiler_ir.py
index ff52641fa273a654f80f02865b41517c419b1f33..0c8a3eee4bd90617d102664614922875abab3e13 100644 (file)
--- a/src/bigint_presentation_code/test_compiler_ir.py
+++ b/src/bigint_presentation_code/test_compiler_ir.py
@@ -1,7 +1,11 @@
 import unittest
 
-from bigint_presentation_code.compiler_ir import (FixedGPRRangeType, Fn, GPRRange, GPRType,
-                                                  Op, OpAddSubE, OpClearCY, OpConcat, OpCopy, OpFuncArg, OpInputMem, OpLI, OpLoad, OpStore,
+from bigint_presentation_code.compiler_ir import (FixedGPRRangeType, Fn,
+                                                  GPRRange, GPRType,
+                                                  OpBigIntAddSub, OpConcat,
+                                                  OpCopy, OpFuncArg,
+                                                  OpInputMem, OpLI, OpLoad,
+                                                  OpSetCA, OpSetVLImm, OpStore,
                                                   op_set_to_list)
 
 
@@ -15,32 +19,41 @@ class TestCompilerIR(unittest.TestCase):
         arg = op1.dest
         op2 = OpInputMem(fn)
         mem = op2.out
-        op3 = OpLoad(fn, arg, offset=0, mem=mem, length=32)
-        a = op3.RT
-        op4 = OpLI(fn, 1)
-        b_0 = op4.out
-        op5 = OpLI(fn, 0, length=31)
-        b_rest = op5.out
-        op6 = OpConcat(fn, [b_0, b_rest])
-        b = op6.dest
-        op7 = OpClearCY(fn)
-        cy = op7.out
-        op8 = OpAddSubE(fn, a, b, cy, is_sub=False)
-        s = op8.RT
-        op9 = OpStore(fn, s, arg, offset=0, mem_in=mem)
-        mem = op9.mem_out
+        op3 = OpSetVLImm(fn, 32)
+        vl = op3.out
+        op4 = OpLoad(fn, arg, offset=0, mem=mem, vl=vl)
+        a = op4.RT
+        op5 = OpLI(fn, 1)
+        b_0 = op5.out
+        op6 = OpSetVLImm(fn, 31)
+        vl = op6.out
+        op7 = OpLI(fn, 0, vl=vl)
+        b_rest = op7.out
+        op8 = OpConcat(fn, [b_0, b_rest])
+        b = op8.dest
+        op9 = OpSetVLImm(fn, 32)
+        vl = op9.out
+        op10 = OpSetCA(fn, False)
+        ca = op10.out
+        op11 = OpBigIntAddSub(fn, a, b, ca, is_sub=False, vl=vl)
+        s = op11.out
+        op12 = OpStore(fn, s, arg, offset=0, mem_in=mem, vl=vl)
+        mem = op12.mem_out
 
         expected_ops = [
-            op7,  # OpClearCY()
-            op5,  # OpLI(0, length=31)
-            op4,  # OpLI(1)
-            op2,  # OpInputMem()
-            op0,  # OpFuncArg(FixedGPRRangeType(GPRRange(3)))
-            op6,  # OpConcat([b_0, b_rest])
-            op1,  # OpCopy(op0.out, GPRType())
-            op3,  # OpLoad(arg, offset=0, mem=mem, length=32)
-            op8,  # OpAddSubE(a, b, cy, is_sub=False)
-            op9,  # OpStore(s, arg, offset=0, mem_in=mem)
+            op10,  # OpSetCA(fn, False)
+            op9,  # OpSetVLImm(fn, 32)
+            op6,  # OpSetVLImm(fn, 31)
+            op5,  # OpLI(fn, 1)
+            op3,  # OpSetVLImm(fn, 32)
+            op2,  # OpInputMem(fn)
+            op0,  # OpFuncArg(fn, FixedGPRRangeType(GPRRange(3)))
+            op7,  # OpLI(fn, 0, vl=vl)
+            op1,  # OpCopy(fn, op0.out, GPRType())
+            op8,  # OpConcat(fn, [b_0, b_rest])
+            op4,  # OpLoad(fn, arg, offset=0, mem=mem, vl=vl)
+            op11,  # OpBigIntAddSub(fn, a, b, ca, is_sub=False, vl=vl)
+            op12,  # OpStore(fn, s, arg, offset=0, mem_in=mem, vl=vl)
         ]
 
         ops = op_set_to_list(fn.ops[::-1])