m.d.comb += ClockSignal("dramsync").eq(ClockSignal("sync"))
m.d.comb += ResetSignal("dramsync").eq(reset_ok)
+ # and a dram 2x sigh
+ cd_dramsync2x = ClockDomain("dramsync2x", local=False)
+ m.domains += cd_dramsync2x
+ m.d.comb += ClockSignal("dramsync2x").eq(ClockSignal("sync2x"))
+ m.d.comb += ResetSignal("dramsync2x").eq(reset_ok)
+
return m