pass in count and num loops to unit test to make it shorter

[ieee754fpu.git] / src / ieee754 / fpmul / test / test_mul.py

diff --git a/src/ieee754/fpmul/test/test_mul.py b/src/ieee754/fpmul/test/test_mul.py
index 21d8252847b01a255837bddd1865aa5ca0a825a0..10fe567484d458570a2987356e8aeaaeb7fd00da 100644 (file)
--- a/src/ieee754/fpmul/test/test_mul.py
+++ b/src/ieee754/fpmul/test/test_mul.py
@@ -6,15 +6,15 @@ from operator import mul
 from nmigen import Module, Signal
 from nmigen.compat.sim import run_simulation
 
-from fmul import FPMUL
+from ieee754.fpmul.fmul import FPMUL
 
-from unit_test_single import (get_mantissa, get_exponent, get_sign, is_nan,
+from ieee754.fpcommon.test.unit_test_single import (get_mantissa, get_exponent, get_sign, is_nan,
                                 is_inf, is_pos_inf, is_neg_inf,
                                 match, get_case, check_case, run_test,
                                 run_edge_cases, run_corner_cases)
 
 
-def testbench(dut):
+def tbench(dut, maxcount, num_loops):
     yield from check_case(dut, 0x40000000, 0x40000000, 0x40800000)
     yield from check_case(dut, 0x41400000, 0x40A00000, 0x42700000)
 
@@ -30,10 +30,13 @@ def testbench(dut):
     print (count, "vectors passed")
 
     yield from run_corner_cases(dut, count, mul, get_case)
-    yield from run_edge_cases(dut, count, mul, get_case)
+    yield from run_edge_cases(dut, count, mul, get_case, maxcount, num_loops)
 
 
-if __name__ == '__main__':
+def test1(maxcount=10, num_loops=5):
     dut = FPMUL(width=32)
-    run_simulation(dut, testbench(dut), vcd_name="test_mul.vcd")
+    run_simulation(dut, tbench(dut, maxcount, num_loops),
+                        vcd_name="test_mul.vcd")
 
+if __name__ == '__main__':
+    test1(maxcount=1000, num_loops=1000)