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update arty a7 clock frequency to 27 mhz, works with QSPI and
[ls2.git]
/
src
/
ls2.py
diff --git
a/src/ls2.py
b/src/ls2.py
index 89d6c06b40565ae7a89166dcbe465c372848bc91..157c1eb38c1f555c3cacb8273f7077227ad44278 100644
(file)
--- a/
src/ls2.py
+++ b/
src/ls2.py
@@
-868,7
+868,7
@@
def build_platform(fpga, firmware):
clk_freq = 50e6
dram_clk_freq = 100e6
if fpga == 'arty_a7':
- clk_freq =
50e6
+ clk_freq =
27e6 # urrr "working" with the QSPI core (25 mhz does not)
if fpga == 'ulx3s':
clk_freq = 40.0e6
if fpga == 'orangecrab':