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[ls2.git] / src / ls2.py

diff --git a/src/ls2.py b/src/ls2.py
index d95335024946bfb3a423be65cfeb366309ed607e..cc55d1998fadbc5c0b395050d98f0e00dc901a36 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -283,7 +283,8 @@ class DDR3SoC(SoC, Elaboratable):
 
         # set up clock request generator
         pod_bits = 25
-        if fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim', 'ulx3s', 'orangecrab']:
+        if fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim', 'ulx3s',
+                    'orangecrab']:
             if fpga in ['isim']:
                 pod_bits = 6
             self.crg = ECP5CRG(clk_freq, dram_clk_freq=None, pod_bits=pod_bits)