Flipped polarity of output enables to match Guava pins logic

[sifive-blocks.git] / src / main / scala / devices / i2c / I2C.scala

diff --git a/src/main/scala/devices/i2c/I2C.scala b/src/main/scala/devices/i2c/I2C.scala
index 543b5917c8063fd947dd8bd0de2912133cac9e8c..0c487642ab5f1fcb473e38bd51a8ebbbebcf3148 100644 (file)
--- a/src/main/scala/devices/i2c/I2C.scala
+++ b/src/main/scala/devices/i2c/I2C.scala
@@ -37,6 +37,7 @@
 
 // This code was re-written in Chisel by SiFive, Inc.
 // See LICENSE for license details.
+// WISHBONE interface replaced by Tilelink2
 
 package sifive.blocks.devices.i2c
 
@@ -181,10 +182,10 @@ trait I2CModule extends Module with HasI2CParameters with HasRegMap {
   }
 
   val sclOen     = Reg(init = true.B)
-  io.port.scl.oe := sclOen
+  io.port.scl.oe := !sclOen
 
   val sdaOen     = Reg(init = true.B)
-  io.port.sda.oe := sdaOen
+  io.port.sda.oe := !sdaOen
 
   val sdaChk     = Reg(init = false.B)       // check SDA output (Multi-master arbitration)