Use HomogenousBag to handle lists of peripherals

[sifive-blocks.git] / src / main / scala / devices / pwm / PWM.scala

diff --git a/src/main/scala/devices/pwm/PWM.scala b/src/main/scala/devices/pwm/PWM.scala
index 2fd870c6797b239dcf8fb636337a707e0f2acc23..d46732cbae2e9f493421efa1588498a160f62406 100644 (file)
--- a/src/main/scala/devices/pwm/PWM.scala
+++ b/src/main/scala/devices/pwm/PWM.scala
@@ -44,21 +44,11 @@ case class PWMConfig(
   regBytes: Int = 4,
   ncmp: Int = 4,
   cmpWidth: Int = 16)
-{
-  val bc = new PWMBundleConfig(ncmp)
-}
-
-case class PWMBundleConfig(
-  ncmp: Int)
-{
-  def union(that: PWMBundleConfig): PWMBundleConfig =
-    PWMBundleConfig(scala.math.max(ncmp, that.ncmp))
-}
 
 trait HasPWMParameters {
-  val params: (PWMConfig, Parameters)
-  val c = params._1
-  implicit val p = params._2
+  implicit val p: Parameters
+  val params: PWMConfig
+  val c = params
 }
 
 trait PWMBundle extends Bundle with HasPWMParameters {
@@ -76,7 +66,7 @@ trait PWMModule extends Module with HasRegMap with HasPWMParameters {
   regmap((GenericTimer.timerRegMap(pwm, 0, c.regBytes)):_*)
 }
 
-class TLPWM(c: PWMConfig)(implicit val p: Parameters)
+class TLPWM(c: PWMConfig)(implicit p: Parameters)
   extends TLRegisterRouter(c.address, interrupts = c.ncmp, size = c.size, beatBytes = p(PeripheryBusConfig).beatBytes)(
-  new TLRegBundle((c, p), _)    with PWMBundle)(
-  new TLRegModule((c, p), _, _) with PWMModule)
+  new TLRegBundle(c, _)    with PWMBundle)(
+  new TLRegModule(c, _, _) with PWMModule)