import Chisel._
import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
-import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
import freechips.rocketchip.util.HeterogeneousBag
-import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.pinctrl.{Pin}
class PWMPortIO(val c: PWMParams) extends Bundle {
val port = Vec(c.ncmp, Bool()).asOutput
override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
}
-class PWMPinsIO(val c: PWMParams) extends Bundle {
- val pwm = Vec(c.ncmp, new GPIOPin)
-}
-
-class PWMGPIOPort(val c: PWMParams) extends Module {
- val io = new Bundle {
- val pwm = new PWMPortIO(c).flip()
- val pins = new PWMPinsIO(c)
- }
-
- GPIOOutputPinCtrl(io.pins.pwm, io.pwm.port.asUInt)
-}
case object PeripheryPWMKey extends Field[Seq[PWMParams]]
}
trait HasPeripheryPWMBundle {
- val pwms: HeterogeneousBag[PWMPortIO]
+ val pwm: HeterogeneousBag[PWMPortIO]
- def PWMtoGPIOPins(dummy: Int = 1): Seq[PWMPinsIO] = pwms.map { p =>
- val pins = Module(new PWMGPIOPort(p.c))
- pins.io.pwm <> p
- pins.io.pins
- }
}
-trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
+trait HasPeripheryPWMModuleImp extends LazyModuleImp with HasPeripheryPWMBundle {
val outer: HasPeripheryPWM
- val pwms = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
+ val pwm = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
- (pwms zip outer.pwms) foreach { case (io, device) =>
+ (pwm zip outer.pwms) foreach { case (io, device) =>
io.port := device.module.io.gpio
}
}