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shiftregs: Use SyncResetSynchronizerShiftReg primitives where appropriate
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
spi
/
SPIPhysical.scala
diff --git
a/src/main/scala/devices/spi/SPIPhysical.scala
b/src/main/scala/devices/spi/SPIPhysical.scala
index 25ad882681e73e42b09a10b7f8a117a942dcce35..0336aef8d06b531d055e8e4c9b321f3bc75995d9 100644
(file)
--- a/
src/main/scala/devices/spi/SPIPhysical.scala
+++ b/
src/main/scala/devices/spi/SPIPhysical.scala
@@
-2,7
+2,7
@@
package sifive.blocks.devices.spi
import Chisel._
-import freechip
chip
s.rocketchip.util.ShiftRegInit
+import freechips.rocketchip.util.ShiftRegInit
class SPIMicroOp(c: SPIParamsBase) extends SPIBundle(c) {
val fn = Bits(width = 1)