uarts.foreach { _.rxd := UInt(1) }
}
- def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTGPIOPort] = uarts.map { u =>
+ def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTPinsIO] = uarts.map { u =>
val pin = Module(new UARTGPIOPort(syncStages))
pin.io.uart <> u
- pin
+ pin.io.pins
}
}