import Chisel._
import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.config.Field
-import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
+import freechips.rocketchip.subsystem.{BaseSubsystem, PeripheryBusKey}
case object PeripheryUARTKey extends Field[Seq[UARTParams]]
-trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
+trait HasPeripheryUART { this: BaseSubsystem =>
private val divinit = (p(PeripheryBusKey).frequency / 115200).toInt
val uartParams = p(PeripheryUARTKey).map(_.copy(divisorInit = divinit))
- val uarts = uartParams map { params =>
- val uart = LazyModule(new TLUART(pbus.beatBytes, params))
- uart.node := pbus.toVariableWidthSlaves
+ val uarts = uartParams.zipWithIndex.map { case(params, i) =>
+ val name = Some(s"uart_$i")
+ val uart = LazyModule(new TLUART(pbus.beatBytes, params)).suggestName(name)
+ pbus.toVariableWidthSlave(name) { uart.node }
ibus.fromSync := uart.intnode
uart
}