import Chisel._
import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
-import freechips.rocketchip.chip.HasSystemNetworks
-import freechips.rocketchip.tilelink.TLFragmenter
-import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
-import sifive.blocks.util.ShiftRegisterInit
case object PeripheryUARTKey extends Field[Seq[UARTParams]]
-trait HasPeripheryUART extends HasSystemNetworks {
- val uartParams = p(PeripheryUARTKey)
+trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
+ private val divinit = (p(PeripheryBusKey).frequency / 115200).toInt
+ val uartParams = p(PeripheryUARTKey).map(_.copy(divisorInit = divinit))
val uarts = uartParams map { params =>
- val uart = LazyModule(new TLUART(peripheryBusBytes, params))
- uart.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
- intBus.intnode := uart.intnode
+ val uart = LazyModule(new TLUART(pbus.beatBytes, params))
+ uart.node := pbus.toVariableWidthSlaves
+ ibus.fromSync := uart.intnode
uart
}
}
io <> device.module.io.port
}
}
-
-class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
- val rxd = pingen()
- val txd = pingen()
-
- def fromUARTPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
- withClockAndReset(clock, reset) {
- txd.outputPin(uart.txd)
- val rxd_t = rxd.inputPin()
- uart.rxd := ShiftRegisterInit(rxd_t, syncStages, Bool(true))
- }
- }
-}
-