move NOT into carrysum so that variable name

[nmigen-gf.git] / src / nmigen_gf / hdl / cldivrem.py

diff --git a/src/nmigen_gf/hdl/cldivrem.py b/src/nmigen_gf/hdl/cldivrem.py
index 01f8c208094796dc9d542a9bbaa80bf71631289c..77c4b1423cccd903637e0f04034a8280f3b2f794 100644 (file)
--- a/src/nmigen_gf/hdl/cldivrem.py
+++ b/src/nmigen_gf/hdl/cldivrem.py
@@ -92,12 +92,12 @@ class EqualLeadingZeroCount(Elaboratable):
         m.d.comb += both_ones.eq(self.a & self.b)
         # `different` is set if there are a different number of leading
         # zeros so far
-        m.d.comb += different.eq(~(self.a ^ self.b))
+        m.d.comb += different.eq(self.a ^ self.b)
 
         # now [ab]use add: the last bit [carry-out] is the result
         csum = Signal(self.width + 1)
         carry_in = 1  # both have no leading zeros so far, so set carry
-        m.d.comb += csum.eq(both_ones + different + carry_in)
+        m.d.comb += csum.eq(both_ones + (~different) + carry_in)
         m.d.comb += self.out.eq(csum[self.width])  # out is carry-out
 
         return m