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[nmigen-gf.git]
/
src
/
nmigen_gf
/
hdl
/
test
/
test_cldivrem.py
diff --git
a/src/nmigen_gf/hdl/test/test_cldivrem.py
b/src/nmigen_gf/hdl/test/test_cldivrem.py
index 4c90e41206e828ebe9e14143bdb4c9f8fd4e3f18..69ed013f16c6e2facd6faf030a2e0c9fd33ac793 100644
(file)
--- a/
src/nmigen_gf/hdl/test/test_cldivrem.py
+++ b/
src/nmigen_gf/hdl/test/test_cldivrem.py
@@
-89,6
+89,7
@@
class TestEqualLeadingZeroCount(FHDLTestCase):
def test_formal_16(self):
# yosys crashes with 32 or 64
+ # https://github.com/YosysHQ/yosys/issues/3268
self.tst_formal(16)
def test_formal_8(self):