# of Horizon 2020 EU Programme 957073.
from functools import reduce
-from operator import xor
+import operator
import unittest
-from nmigen.hdl.ast import (AnyConst, Assert, Signal, Const, unsigned, signed,
- Mux)
+from nmigen.hdl.ast import AnyConst, Assert, Signal, Const, unsigned, Mux
from nmigen.hdl.dsl import Module
from nmutil.formaltest import FHDLTestCase
from nmigen_gf.reference.clmul import clmul
-from nmigen_gf.hdl.clmul import BitwiseXorReduce, CLMulAdd
+from nmigen_gf.hdl.clmul import CLMulAdd
from nmigen.sim import Delay
from nmutil.sim_util import do_sim, hash_256
-class TestBitwiseXorReduce(FHDLTestCase):
- def tst(self, input_shapes):
- dut = BitwiseXorReduce(Signal(w, name=f"input_{i}")
- for i, w in enumerate(input_shapes))
- self.assertEqual(reduce(xor, dut.input_values).shape(),
- dut.output.shape())
-
- def case(inputs):
- expected = reduce(xor, inputs)
- with self.subTest(inputs=list(map(hex, inputs)),
- expected=hex(expected)):
- for i, inp in enumerate(inputs):
- yield dut.input_values[i].eq(inp)
- yield Delay(1e-6)
- output = yield dut.output
- with self.subTest(output=hex(output)):
- self.assertEqual(expected, output)
-
- def process():
- for i in range(100):
- inputs = []
- for inp in dut.input_values:
- v = hash_256(f"bxorr input {i} {inp.name}")
- inputs.append(Const.normalize(v, inp.shape()))
- yield from case(inputs)
-
- with do_sim(self, dut, [*dut.input_values, dut.output]) as sim:
- sim.add_process(process)
- sim.run()
-
- def tst_formal(self, input_shapes):
- dut = BitwiseXorReduce(Signal(w, name=f"input_{i}")
- for i, w in enumerate(input_shapes))
- m = Module()
- m.submodules.dut = dut
- for i in dut.input_values:
- m.d.comb += i.eq(AnyConst(i.shape()))
- m.d.comb += Assert(dut.output == reduce(xor, dut.input_values))
- self.assertFormal(m)
-
- def test_65_of_u64(self):
- self.tst([64] * 65)
-
- def test_formal_65_of_u64(self):
- self.tst_formal([64] * 65)
-
- def test_5_of_u6(self):
- self.tst([6] * 5)
-
- def test_formal_5_of_u6(self):
- self.tst_formal([6] * 5)
-
- def test_u5_i6_u3_i10(self):
- self.tst([unsigned(5), signed(6), unsigned(3), signed(10)])
-
- def test_formal_u5_i6_u3_i10(self):
- self.tst_formal([unsigned(5), signed(6), unsigned(3), signed(10)])
-
-
class TestCLMulAdd(FHDLTestCase):
def tst(self, factor_width, terms_width):
dut = CLMulAdd(factor_width, terms_width)
max((factor_width * 2 - 1, *terms_width)))
def case(factor1, factor2, terms):
- expected = reduce(xor, terms, clmul(factor1, factor2))
+ expected = reduce(operator.xor, terms, clmul(factor1, factor2))
with self.subTest(factor1=hex(factor1),
factor2=bin(factor2),
terms=list(map(hex, terms)),
sig = Signal(reduce_inputs[i].shape(), name=f"reduce_input_{i}")
m.d.comb += sig.eq(reduce_inputs[i])
reduce_inputs[i] = sig
- expected = Signal(reduce(xor, reduce_inputs).shape())
- m.d.comb += expected.eq(reduce(xor, reduce_inputs))
+ expected = Signal(reduce(operator.xor, reduce_inputs).shape())
+ m.d.comb += expected.eq(reduce(operator.xor, reduce_inputs))
m.d.comb += Assert(dut.output == expected)
self.assertFormal(m)