move writing rtlil into do_sim

[nmutil.git] / src / nmutil / lut.py

diff --git a/src/nmutil/lut.py b/src/nmutil/lut.py
index 8e8a18a7c4c5c99b815dcbc0bdcc05e1947cbde3..4eb790d4e11c843aec4e4678735b15fd9f777e05 100644 (file)
--- a/src/nmutil/lut.py
+++ b/src/nmutil/lut.py
@@ -144,9 +144,5 @@ class TreeBitwiseLut(Elaboratable):
         return [self.input, self.chunk_sizes, self.output]
 
 
-# useful to see what is going on: use yosys "read_ilang test_lut.il; show top"
-if __name__ == '__main__':
-    dut = BitwiseLut(3, 8)
-    vl = rtlil.convert(dut, ports=dut.ports())
-    with open("test_lut.il", "w") as f:
-        f.write(vl)
+# useful to see what is going on:
+# yosys <<<"read_ilang sim_test_out/__main__.TestBitwiseLut.test_tree/0.il; proc;;; show top"