resolve awful meta-class hacking (with thanks to jsbueno on stackexchange)

[ieee754fpu.git] / src / nmutil / singlepipe.py

diff --git a/src/nmutil/singlepipe.py b/src/nmutil/singlepipe.py
index 68b62e432d4fc6022b99361c3358d01638414fce..8a5b06dcaa41cb043d175f65beb34716a0f3fbea 100644 (file)
--- a/src/nmutil/singlepipe.py
+++ b/src/nmutil/singlepipe.py
@@ -132,13 +132,13 @@ from nmigen import Signal, Mux, Module, Elaboratable
 from nmigen.cli import verilog, rtlil
 from nmigen.hdl.rec import Record
 
-from queue import Queue
+from nmutil.queue import Queue
 import inspect
 
-from iocontrol import (PrevControl, NextControl, Object, RecordObject)
-from stageapi import (_spec, StageCls, Stage, StageChain, StageHelper)
-import nmoperator
-                      
+from nmutil.iocontrol import (PrevControl, NextControl, Object, RecordObject)
+from nmutil.stageapi import (_spec, StageCls, Stage, StageChain, StageHelper)
+from nmutil import nmoperator
+
 
 class RecordBasedStage(Stage):
     """ convenience class which provides a Records-based layout.
@@ -190,6 +190,7 @@ class ControlBase(StageHelper, Elaboratable):
             * add data_o member to NextControl (n)
             Calling ControlBase._new_data is a good way to do that.
         """
+        print ("ControlBase", self, stage, in_multi, stage_ctl)
         StageHelper.__init__(self, stage)
 
         # set up input and output IO ACK (prev/next ready/valid)