format code

[nmutil.git] / src / nmutil / test / example_buf_pipe.py

diff --git a/src/nmutil/test/example_buf_pipe.py b/src/nmutil/test/example_buf_pipe.py
index 61e9b1346e5cb1cf7402dd27b1393561cd710b0c..823a999b52052a7a11e5ddb1c845b127f1ffae22 100644 (file)
--- a/src/nmutil/test/example_buf_pipe.py
+++ b/src/nmutil/test/example_buf_pipe.py
@@ -4,8 +4,8 @@
 from nmutil.nmoperator import eq
 from nmutil.iocontrol import (PrevControl, NextControl)
 from nmutil.singlepipe import (PrevControl, NextControl, ControlBase,
-                        StageCls, Stage, StageChain,
-                        BufferedHandshake, UnbufferedPipeline)
+                               StageCls, Stage, StageChain,
+                               BufferedHandshake, UnbufferedPipeline)
 
 from nmigen import Signal, Module
 from nmigen.cli import verilog, rtlil