bug 1236: add extra argument to svstep: RA.

[openpower-isa.git] / src / openpower / decoder / isa / test_caller_svp64_bc.py

diff --git a/src/openpower/decoder/isa/test_caller_svp64_bc.py b/src/openpower/decoder/isa/test_caller_svp64_bc.py
index 36e4bd0bfc176fe310d409c159b7d8d7d767a635..25ade2f8de4ee3ede84dfe700e8a8808153cb95e 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_bc.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_bc.py
@@ -316,7 +316,7 @@ class DecoderTestCase(FHDLTestCase):
                 "setvl 0, 0, %d, 1, 1, 1" % maxvl, # VL = MAXVL = 2, vf=1
                 "sv.cmpi *cr0, 1, *10, 0x10", # compare reg val with immediate
                 "sv.bc 0, *2, 0x10", # jmp if CTR!=0 AND reg not equal to imm
-                "svstep. 27, 1, 0",
+                "svstep. 27, 0, 1, 0",
                 "bc 4, 3, -0x14", # CR_BI=0, jump to start of loop (sv.cmpi)
                 "or 0, 0, 0", # jump to here if terminate VF loop early
             ]