bug 1236: add extra argument to svstep: RA.

[openpower-isa.git] / src / openpower / decoder / isa / test_caller_svp64_dct.py

diff --git a/src/openpower/decoder/isa/test_caller_svp64_dct.py b/src/openpower/decoder/isa/test_caller_svp64_dct.py
index 581b35223e06ebc6d44e160bb1b7695536c367d0..96674d4a451c4046829bf0cb54a0044d06ea8668 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_dct.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_dct.py
@@ -438,8 +438,8 @@ class DCTTestCase(FHDLTestCase):
         """
         lst = SVP64Asm(["svshape 8, 1, 1, 5, 0",
                         "svremap 0, 0, 0, 2, 0, 1, 1",
-                        "sv.svstep *4, 3, 1",  # svstep get vector of ci
-                        "sv.svstep *16, 2, 1",  # svstep get vector of step
+                        "sv.svstep *4, 0, 3, 1",  # svstep get vector of ci
+                        "sv.svstep *16, 0, 2, 1",  # svstep get vector of step
                         "addi 1, 0, 0x0000",
                         "setvl 0, 0, 7, 0, 1, 1",
                         "sv.std *4, 0(1)",