bug 1236: add extra argument to svstep: RA.

[openpower-isa.git] / src / openpower / decoder / isa / test_caller_svstate.py

diff --git a/src/openpower/decoder/isa/test_caller_svstate.py b/src/openpower/decoder/isa/test_caller_svstate.py
index 48c4b6f24d87eed99520198ca60576b23e4997f7..88e77a7dc06814c848f01a49516710246f449de6 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svstate.py
+++ b/src/openpower/decoder/isa/test_caller_svstate.py
@@ -60,10 +60,10 @@ class SVSTATETestCase(FHDLTestCase):
         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
                         'sv.add 1, *5, *9',
                         'sv.addi *12, 1, 1',
-                        "svstep. 0, 1, 0",
+                        "svstep. 0, 0, 1, 0",
                         'sv.add 1, *5, *9',
                         'sv.addi *12, 1, 1',
-                        "svstep. 0, 1, 0",
+                        "svstep. 0, 0, 1, 0",
                         ])
 
         sequence is as follows:
@@ -92,10 +92,10 @@ class SVSTATETestCase(FHDLTestCase):
         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
                         'sv.add 1, *5, *9',       # scalar dest (into r1)
                         'sv.addi *12, 1, 1',       # scalar src (from r1)
-                        "svstep. 0, 1, 0",  # svstep
+                        "svstep. 0, 0, 1, 0",  # svstep
                         'sv.add 1, *5, *9',       # again, scalar dest
                         'sv.addi *12, 1, 1',       # but vector dest
-                        "svstep. 0, 1, 0",  # svstep (end: sets CR0.SO)
+                        "svstep. 0, 0, 1, 0",  # svstep (end: sets CR0.SO)
                         ])
         lst = list(lst)