> Data Read phase is on posedge and Data write is on negdege
-- send the received arid and bid's so that DMA can identify. duplicate instead of extend
*/
+ import GetPut::*;
import TriState::*;
import ConcatReg ::*;
import Semi_FIFOF :: *;
endinterface;
interface ncs_o = interface Get
method ActionValue#(Bit#(1)) get;
- return ncs
+ return ncs;
endmethod
endinterface;
endinterface