add always_ready to getput on lcd

[shakti-peripherals.git] / src / peripherals / rgbttl / rgbttl_dummy.bsv

diff --git a/src/peripherals/rgbttl/rgbttl_dummy.bsv b/src/peripherals/rgbttl/rgbttl_dummy.bsv
index 4d3b66b63ee3adf9c2c64c36f306a16f302dc002..35598d324729affd34701527c59ba2944c748585 100644 (file)
--- a/src/peripherals/rgbttl/rgbttl_dummy.bsv
+++ b/src/peripherals/rgbttl/rgbttl_dummy.bsv
@@ -31,25 +31,26 @@ Details:
 package rgbttl_dummy;
   `define RGBTTL_WIDTH 18
   `include "instance_defines.bsv"
-  import ClockDiv::*;
-  import ConcatReg::*;
-  import Semi_FIFOF::*;
+  import GetPut::*;
   import BUtils ::*;
-  import AXI4_Lite_Types::*;
+  import AXI4_Types::*;
 
   interface Ifc_rgbttl_dummy;
-         interface AXI4_Lite_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;
-      interface Get#(Bit#(1)) de;
-      interface Get#(Bit#(1)) ck;
-      interface Get#(Bit#(1)) vs;
-      interface Get#(Bit#(1)) hs;
-      interface Get#(Bit#(`RGBTTL_WIDTH)) data_out;
+           interface AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
+           interface AXI4_Slave_IFC#(`PADDR, `DATA, `USERSPACE) slave;
+      (* always_ready *) interface Get#(Bit#(1)) de;
+      (* always_ready *) interface Get#(Bit#(1)) ck;
+      (* always_ready *) interface Get#(Bit#(1)) vs;
+      (* always_ready *) interface Get#(Bit#(1)) hs;
+      (* always_ready *) interface Get#(Bit#(`RGBTTL_WIDTH)) data_out;
   endinterface
 
   (*synthesize*)
   module mkrgbttl_dummy(Ifc_rgbttl_dummy);
-               AXI4_Lite_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
-                            s_xactor<-mkAXI4_Lite_Slave_Xactor();
+               AXI4_Slave_Xactor_IFC#(`PADDR,`DATA, `USERSPACE)
+                            s_xactor<-mkAXI4_Slave_Xactor();
+               AXI4_Master_Xactor_IFC#(`PADDR,`DATA, `USERSPACE)
+                            m_xactor<-mkAXI4_Master_Xactor();
 
       Reg#(Bit#(1)) rg_de <- mkReg(0);
       Reg#(Bit#(1)) rg_ck <- mkReg(0);
@@ -81,12 +82,13 @@ package rgbttl_dummy;
         endmethod
       endinterface;
 
-      interface data = interface Get
+      interface data_out = interface Get
         method ActionValue#(Bit#(`RGBTTL_WIDTH)) get;
-          return data_out;
+          return rg_data;
         endmethod
       endinterface;
 
       interface slave=s_xactor.axi_side;
+      interface master=m_xactor.axi_side;
   endmodule
 endpackage