`define RGBTTL_WIDTH 18
`include "instance_defines.bsv"
import GetPut::*;
- import ClockDiv::*;
- import ConcatReg::*;
- import Semi_FIFOF::*;
import BUtils ::*;
import AXI4_Types::*;
interface Ifc_rgbttl_dummy;
- interface AXI4_Master_IFC#(`ADDR, `DATA, `USERSPACE) master;
- interface Get#(Bit#(1)) de;
- interface Get#(Bit#(1)) ck;
- interface Get#(Bit#(1)) vs;
- interface Get#(Bit#(1)) hs;
- interface Get#(Bit#(`RGBTTL_WIDTH)) data_out;
+ interface AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
+ interface AXI4_Slave_IFC#(`PADDR, `DATA, `USERSPACE) slave;
+ (* always_ready *) interface Get#(Bit#(1)) de;
+ (* always_ready *) interface Get#(Bit#(1)) ck;
+ (* always_ready *) interface Get#(Bit#(1)) vs;
+ (* always_ready *) interface Get#(Bit#(1)) hs;
+ (* always_ready *) interface Get#(Bit#(`RGBTTL_WIDTH)) data_out;
endinterface
(*synthesize*)
module mkrgbttl_dummy(Ifc_rgbttl_dummy);
- AXI4_Lite_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
- s_xactor<-mkAXI4_Lite_Slave_Xactor();
+ AXI4_Slave_Xactor_IFC#(`PADDR,`DATA, `USERSPACE)
+ s_xactor<-mkAXI4_Slave_Xactor();
+ AXI4_Master_Xactor_IFC#(`PADDR,`DATA, `USERSPACE)
+ m_xactor<-mkAXI4_Master_Xactor();
Reg#(Bit#(1)) rg_de <- mkReg(0);
Reg#(Bit#(1)) rg_ck <- mkReg(0);
endmethod
endinterface;
- interface master=s_xactor.axi_side;
+ interface slave=s_xactor.axi_side;
+ interface master=m_xactor.axi_side;
endmodule
endpackage