--------------------------------------------------------------------------------------------------
*/
package rgbttl_dummy;
+ `define RGBTTL_WIDTH 18
`include "instance_defines.bsv"
+ import GetPut::*;
import ClockDiv::*;
import ConcatReg::*;
import Semi_FIFOF::*;
import BUtils ::*;
- import AXI4_Lite_Types::*;
+ import AXI4_Types::*;
- interface Ifc_rgbttl_dummy#(numeric type buswidth);
- interface AXI4_Lite_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;
- method Bit#(1) de;
- method Bit#(1) ck;
- method Bit#(1) vs;
- method Bit#(1) hs;
- method Bit#(buswidth) data;
+ interface Ifc_rgbttl_dummy;
+ interface AXI4_Master_IFC#(`ADDR, `DATA, `USERSPACE) master;
+ interface Get#(Bit#(1)) de;
+ interface Get#(Bit#(1)) ck;
+ interface Get#(Bit#(1)) vs;
+ interface Get#(Bit#(1)) hs;
+ interface Get#(Bit#(`RGBTTL_WIDTH)) data_out;
endinterface
(*synthesize*)
- module mkrgbttl_dummy(Ifc_rgbttl_dummy#(buswidth))
+ module mkrgbttl_dummy(Ifc_rgbttl_dummy);
AXI4_Lite_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
s_xactor<-mkAXI4_Lite_Slave_Xactor();
- let v_buswidth = valueOf(v_buswidth);
Reg#(Bit#(1)) rg_de <- mkReg(0);
Reg#(Bit#(1)) rg_ck <- mkReg(0);
Reg#(Bit#(1)) rg_vs <- mkReg(0);
Reg#(Bit#(1)) rg_hs <- mkReg(0);
- Reg#(Bit#(v_buswidth)) rg_data;
- for(Integer i = 0; i < v_no_of_ir_pins;i=i+1) begin
- rg_data[i] <- mkReg(0);
- end
+ Reg#(Bit#(`RGBTTL_WIDTH)) rg_data <- mkReg(0);
- method de = rg_de;
- method ck = rg_ck;
- method vs = rg_vs;
- method hs = rg_hs;
- method data = rg_data;
- interface slave=s_xactor.axi_side;
+ interface de = interface Get
+ method ActionValue#(Bit#(1)) get;
+ return rg_de;
+ endmethod
+ endinterface;
+
+ interface ck = interface Get
+ method ActionValue#(Bit#(1)) get;
+ return rg_ck;
+ endmethod
+ endinterface;
+
+ interface vs = interface Get
+ method ActionValue#(Bit#(1)) get;
+ return rg_vs;
+ endmethod
+ endinterface;
+
+ interface hs = interface Get
+ method ActionValue#(Bit#(1)) get;
+ return rg_hs;
+ endmethod
+ endinterface;
+
+ interface data_out = interface Get
+ method ActionValue#(Bit#(`RGBTTL_WIDTH)) get;
+ return rg_data;
+ endmethod
+ endinterface;
+
+ interface master=s_xactor.axi_side;
endmodule
endpackage