experimenting with cscore, overlapping instructions

[soc.git] / src / regfile / regfile.py

diff --git a/src/regfile/regfile.py b/src/regfile/regfile.py
index 29fbda65b14ad4546e264f3a57f31af06389c900..1d732ba87a78ad6bb37f4a731b39a5495e9335bd 100644 (file)
--- a/src/regfile/regfile.py
+++ b/src/regfile/regfile.py
@@ -10,7 +10,7 @@ import operator
 
 
 class Register(Elaboratable):
-    def __init__(self, width, writethru=False):
+    def __init__(self, width, writethru=True):
         self.width = width
         self.writethru = writethru
         self._rdports = []