move IRQLine out because that makes soc dependent on LambdaSOC

[soc.git] / src / soc / bus / opencores_ethmac.py

diff --git a/src/soc/bus/opencores_ethmac.py b/src/soc/bus/opencores_ethmac.py
index 5720c1ce65ce4cc06b920f30e5c800c1cfa5b3ca..cad49194583c3faf4cb974c4c635bf53d4a8fe85 100644 (file)
--- a/src/soc/bus/opencores_ethmac.py
+++ b/src/soc/bus/opencores_ethmac.py
@@ -13,7 +13,6 @@ from nmigen import (Elaboratable, Cat, Module, Signal, ClockSignal, Instance,
 
 from nmigen_soc.wishbone.bus import Interface
 from nmigen_soc.memory import MemoryMap
-from lambdasoc.periph.event import IRQLine
 from nmigen.utils import log2_int
 from nmigen.cli import rtlil, verilog
 import os
@@ -55,7 +54,7 @@ class EthMAC(Elaboratable):
         self.master_bus = master_bus
         self.slave_bus = slave_bus
         if irq is None:
-            irq = IRQLine()
+            irq = Signal()
         self.irq = irq
 
         slave_mmap = MemoryMap(addr_width=12+self.dsize,