from nmutil.latch import SRLatch, latchregister
from nmutil.iocontrol import RecordObject
+from nmutil.util import rising_edge
from soc.fu.regspec import RegSpec, RegSpecALUAPI
def go_record(n, name):
- r = Record([('go', n, DIR_FANIN),
- ('rel', n, DIR_FANOUT)], name=name)
- r.go.reset_less = True
- r.rel.reset_less = True
+ r = Record([('go_i', n, DIR_FANIN),
+ ('rel_o', n, DIR_FANOUT)], name=name)
+ r.go_i.reset_less = True
+ r.rel_o.reset_less = True
return r
self.oper_i = subkls(name="oper_i_%s" % name) # operand
# create read/write and other scoreboard signalling
- self.rd = go_record(n_src, name="rd") # read in, req out
- self.wr = go_record(n_dst, name="wr") # write in, req out
- self.rdmaskn = Signal(n_src, reset_less=True) # read mask
- self.wrmask = Signal(n_dst, reset_less=True) # write mask
- self.issue_i = Signal(reset_less=True) # fn issue in
- self.shadown_i = Signal(reset=1) # shadow function, defaults to ON
- self.go_die_i = Signal() # go die (reset)
+ self.rd = go_record(n_src, name="cu_rd") # read in, req out
+ self.wr = go_record(n_dst, name="cu_wr") # write in, req out
+ # read / write mask
+ self.rdmaskn = Signal(n_src, name="cu_rdmaskn_i", reset_less=True)
+ self.wrmask = Signal(n_dst, name="cu_wrmask_o", reset_less=True)
+
+ # fn issue in
+ self.issue_i = Signal(name="cu_issue_i", reset_less=True)
+ # shadow function, defaults to ON
+ self.shadown_i = Signal(name="cu_shadown_i", reset=1)
+ # go die (reset)
+ self.go_die_i = Signal(name="cu_go_die_i")
# output (busy/done)
- self.busy_o = Signal(reset_less=True) # fn busy out
- self.done_o = Signal(reset_less=True)
+ self.busy_o = Signal(name="cu_busy_o", reset_less=True) # fn busy out
+ self.done_o = Signal(name="cu_done_o", reset_less=True)
+ self.alu_done_o = Signal(name="cu_alu_done_o", reset_less=True)
class MultiCompUnit(RegSpecALUAPI, Elaboratable):
- def __init__(self, rwid, alu, opsubsetkls, n_src=2, n_dst=1, name=None):
+ def __init__(self, rwid, alu, opsubsetkls, n_src=2, n_dst=1, name=None,
+ sync_rw=True):
"""MultiCompUnit
* :rwid: width of register latches (TODO: allocate per regspec)
* :n_dst: number of destination operands
"""
RegSpecALUAPI.__init__(self, rwid, alu)
+ self.sync_rw = sync_rw
self.alu_name = name or "alu"
self.opsubsetkls = opsubsetkls
self.cu = cu = CompUnitRecord(opsubsetkls, rwid, n_src, n_dst,
self.wr = cu.wr
self.rdmaskn = cu.rdmaskn
self.wrmask = cu.wrmask
- self.go_rd_i = self.rd.go # temporary naming
- self.go_wr_i = self.wr.go # temporary naming
- self.rd_rel_o = self.rd.rel # temporary naming
- self.req_rel_o = self.wr.rel # temporary naming
+ self.alu_done_o = cu.alu_done_o
+ self.go_rd_i = self.rd.go_i # temporary naming
+ self.go_wr_i = self.wr.go_i # temporary naming
+ self.rd_rel_o = self.rd.rel_o # temporary naming
+ self.req_rel_o = self.wr.rel_o # temporary naming
self.issue_i = cu.issue_i
self.shadown_i = cu.shadown_i
self.go_die_i = cu.go_die_i
self.busy_o = cu.busy_o
self.dest = cu._dest
- self.data_o = self.dest[0] # Dest out
+ self.o_data = self.dest[0] # Dest out
self.done_o = cu.done_o
def _mux_op(self, m, sl, op_is_imm, imm, i):
# to trigger *from* the opcode latch instead.
src_or_imm = Signal(self.cu._get_srcwid(i), reset_less=True)
src_sel = Signal(reset_less=True)
- m.d.comb += src_sel.eq(Mux(op_is_imm, self.opc_l.q, self.src_l.q[i]))
+ m.d.comb += src_sel.eq(Mux(op_is_imm, self.opc_l.q, sl[i][2]))
m.d.comb += src_or_imm.eq(Mux(op_is_imm, imm, self.src_i[i]))
# overwrite 1st src-latch with immediate-muxed stuff
sl[i][0] = src_or_imm
def elaborate(self, platform):
m = Module()
- setattr(m.submodules, self.alu_name, self.alu)
+ if self.sync_rw:
+ rw_domain = m.d.sync
+ else:
+ rw_domain = m.d.comb
+ # generate a pulse on system reset, to reset any latches, if needed
+ system_reset = Signal(reset=1)
+ m.d.sync += system_reset.eq(0)
+
+ # add the ALU to the MultiCompUnit only if it is a "real" ALU
+ # see AllFunctionUnits as to why: a FunctionUnitBaseMulti
+ # only has one "real" ALU but multiple pseudo front-ends,
+ # aka "ReservationStations" (ALUProxy "fronts")
+ if isinstance(self.alu, Elaboratable):
+ setattr(m.submodules, self.alu_name, self.alu)
m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
m.submodules.req_l = req_l = SRLatch(False, self.n_dst, name="req")
# ALU only proceeds when all src are ready. rd_rel_o is delayed
# so combine it with go_rd_i. if all bits are set we're good
all_rd = Signal(reset_less=True)
- m.d.comb += all_rd.eq(self.busy_o & rok_l.q &
- (((~self.rd.rel) | self.rd.go).all()))
+ m.d.comb += all_rd.eq(self.busy_o & # rok_l.q & # XXX LOOP
+ (((~self.rd.rel_o) | self.rd.go_i).all()))
# generate read-done pulse
- all_rd_dly = Signal(reset_less=True)
all_rd_pulse = Signal(reset_less=True)
- m.d.sync += all_rd_dly.eq(all_rd)
- m.d.comb += all_rd_pulse.eq(all_rd & ~all_rd_dly)
+ m.d.comb += all_rd_pulse.eq(rising_edge(m, all_rd)) # XXX LOOP
# create rising pulse from alu valid condition.
- alu_done = Signal(reset_less=True)
- alu_done_dly = Signal(reset_less=True)
+ alu_done = self.cu.alu_done_o
alu_pulse = Signal(reset_less=True)
alu_pulsem = Signal(self.n_dst, reset_less=True)
- m.d.comb += alu_done.eq(self.alu.n.valid_o)
- m.d.sync += alu_done_dly.eq(alu_done)
- m.d.comb += alu_pulse.eq(alu_done & ~alu_done_dly)
+ m.d.comb += alu_done.eq(self.alu.n.o_valid)
+ m.d.comb += alu_pulse.eq(rising_edge(m, alu_done))
m.d.comb += alu_pulsem.eq(Repl(alu_pulse, self.n_dst))
# sigh bug where req_l gets both set and reset raised at same time
prev_wr_go = Signal(self.n_dst)
brd = Repl(self.busy_o, self.n_dst)
- m.d.sync += prev_wr_go.eq(self.wr.go & brd)
+ m.d.sync += prev_wr_go.eq(self.wr.go_i & brd)
# write_requests all done
# req_done works because any one of the last of the writes
# is enough, when combined with when read-phase is done (rst_l.q)
wr_any = Signal(reset_less=True)
req_done = Signal(reset_less=True)
- m.d.comb += self.done_o.eq(self.busy_o &
- ~((self.wr.rel & ~self.wrmask).bool()))
- m.d.comb += wr_any.eq(self.wr.go.bool() | prev_wr_go.bool())
- m.d.comb += req_done.eq(wr_any & ~self.alu.n.ready_i &
- ((req_l.q & self.wrmask) == 0))
+ m.d.comb += self.done_o.eq(self.busy_o & ~(self.wr.rel_o).bool())
+ m.d.comb += wr_any.eq(self.wr.go_i.bool() | prev_wr_go.bool())
+ m.d.comb += req_done.eq(wr_any & ~self.alu.n.i_ready & (req_l.q == 0))
# argh, complicated hack: if there are no regs to write,
# instead of waiting for regs that are never going to happen,
# we indicate "done" when the ALU is "done"
with m.If((self.wrmask == 0) &
- self.alu.n.ready_i & self.alu.n.valid_o & self.busy_o):
+ self.alu.n.i_ready & self.alu.n.o_valid & self.busy_o):
m.d.comb += req_done.eq(1)
# shadow/go_die
reset_r = Signal(self.n_src, reset_less=True)
m.d.comb += reset.eq(req_done | self.go_die_i)
m.d.comb += rst_r.eq(self.issue_i | self.go_die_i)
- m.d.comb += reset_w.eq(self.wr.go | Repl(self.go_die_i, self.n_dst))
- m.d.comb += reset_r.eq(self.rd.go | Repl(self.go_die_i, self.n_src))
+ m.d.comb += reset_w.eq(self.wr.go_i | Repl(self.go_die_i, self.n_dst))
+ m.d.comb += reset_r.eq(self.rd.go_i | Repl(rst_r, self.n_src))
# read-done,wr-proceed latch
- m.d.comb += rok_l.s.eq(self.issue_i) # set up when issue starts
- m.d.sync += rok_l.r.eq(self.alu.n.valid_o & self.busy_o) # ALU done
+ rw_domain += rok_l.s.eq(self.issue_i) # set up when issue starts
+ rw_domain += rok_l.r.eq(self.alu.n.o_valid & self.busy_o) # ALUdone LOOP
# wr-done, back-to-start latch
- m.d.comb += rst_l.s.eq(all_rd) # set when read-phase is fully done
- m.d.comb += rst_l.r.eq(rst_r) # *off* on issue
+ rw_domain += rst_l.s.eq(all_rd) # set when read-phase is fully done
+ rw_domain += rst_l.r.eq(rst_r) # *off* on issue
# opcode latch (not using go_rd_i) - inverted so that busy resets to 0
m.d.sync += opc_l.s.eq(self.issue_i) # set on issue
m.d.sync += opc_l.r.eq(req_done) # reset on ALU
- # src operand latch (not using go_wr_i)
- m.d.sync += src_l.s.eq(Repl(self.issue_i, self.n_src))
+ # src operand latch (not using go_wr_i) ANDed with rdmask
+ rdmaskn = Signal(self.n_src)
+ latchregister(m, self.rdmaskn, rdmaskn, self.issue_i, name="rdmask_l")
+ m.d.sync += src_l.s.eq(Repl(self.issue_i, self.n_src) & ~rdmaskn)
m.d.sync += src_l.r.eq(reset_r)
# dest operand latch (not using issue_i)
- m.d.comb += req_l.s.eq(alu_pulsem & self.wrmask)
- m.d.comb += req_l.r.eq(reset_w | prev_wr_go)
+ rw_domain += req_l.s.eq(alu_pulsem & self.wrmask)
+ m.d.comb += req_l.r.eq(reset_w | prev_wr_go |
+ Repl(system_reset, self.n_dst))
- # create a latch/register for the operand
- oper_r = self.opsubsetkls(name="oper_r")
- latchregister(m, self.oper_i, oper_r, self.issue_i, "oper_l")
+ # pass operation to the ALU (sync: plenty time to wait for src reads)
+ op = self.get_op()
+ with m.If(self.issue_i):
+ m.d.sync += op.eq(self.oper_i)
# and for each output from the ALU: capture when ALU output is valid
drl = []
name = "data_r%d" % i
lro = self.get_out(i)
ok = Const(1, 1)
+ data_r_ok = Const(1, 1)
if isinstance(lro, Record):
+ print("wr fields", i, lro, lro.fields)
data_r = Record.like(lro, name=name)
- print("wr fields", i, lro, data_r.fields)
# bye-bye abstract interface design..
- fname = find_ok(data_r.fields)
+ fname = find_ok(lro.fields)
if fname:
- ok = data_r[fname]
+ ok = getattr(lro, fname)
+ data_r_ok = getattr(data_r, fname)
+ # write-ok based on incoming output *and* whether the latched
+ # data was ok.
+ # XXX fails - wrok.append((ok|data_r_ok) & self.busy_o)
+ wrok.append(ok & self.busy_o)
else:
- data_r = Signal.like(lro, name=name, reset_less=True)
- wrok.append(ok & self.busy_o)
- latchregister(m, lro, data_r, alu_pulsem, name + "_l")
+ data_r = Signal.like(lro, name=name)
+ # really should retire this but it's part of unit tests
+ wrok.append(ok & self.busy_o)
+ #latchregister(m, lro, data_r, ok & self.busy_o, name=name)
+ latchregister(m, lro, data_r, alu_pulse, name=name)
+ with m.If(self.issue_i):
+ m.d.comb += data_r.eq(0)
drl.append(data_r)
# ok, above we collated anything with an "ok" on the output side
# a regfile port because this particular output is not valid"
m.d.comb += self.wrmask.eq(Cat(*wrok))
- # pass the operation to the ALU
- m.d.comb += self.get_op().eq(oper_r)
-
# create list of src/alu-src/src-latch. override 1st and 2nd one below.
# in the case, for ALU and Logical pipelines, we assume RB is the
# 2nd operand in the input "regspec". see for example
# if the operand subset has "zero_a" we implicitly assume that means
# src_i[0] is an INT reg type where zero can be multiplexed in, instead.
# see https://bugs.libre-soc.org/show_bug.cgi?id=336
- if hasattr(oper_r, "zero_a"):
+ if hasattr(op, "zero_a"):
# select zero imm if opcode says so. however also change the latch
# to trigger *from* the opcode latch instead.
- self._mux_op(m, sl, oper_r.zero_a, 0, 0)
+ self._mux_op(m, sl, op.zero_a, 0, 0)
# if the operand subset has "imm_data" we implicitly assume that means
# "this is an INT ALU/Logical FU jobbie, RB is muxed with the immediate"
- if hasattr(oper_r, "imm_data"):
+ if hasattr(op, "imm_data"):
# select immediate if opcode says so. however also change the latch
# to trigger *from* the opcode latch instead.
- op_is_imm = oper_r.imm_data.imm_ok
- imm = oper_r.imm_data.imm
+ op_is_imm = op.imm_data.ok
+ imm = op.imm_data.data
self._mux_op(m, sl, op_is_imm, imm, 1)
# create a latch/register for src1/src2 (even if it is a copy of imm)
for i in range(self.n_src):
src, alusrc, latch, _ = sl[i]
- latchregister(m, src, alusrc, latch, name="src_r%d" % i)
+ reg = latchregister(m, src, alusrc, latch, name="src_r%d" % i)
+ # rdmask stops src latches from being set. clear all if not busy
+ with m.If(~self.busy_o):
+ m.d.sync += reg.eq(0)
# -----
# ALU connection / interaction
# on a go_read, tell the ALU we're accepting data.
m.submodules.alui_l = alui_l = SRLatch(False, name="alui")
- m.d.comb += self.alu.p.valid_i.eq(alui_l.q)
- m.d.sync += alui_l.r.eq(self.alu.p.ready_o & alui_l.q)
+ m.d.comb += self.alu.p.i_valid.eq(alui_l.q)
+ m.d.sync += alui_l.r.eq(self.alu.p.o_ready & alui_l.q)
m.d.comb += alui_l.s.eq(all_rd_pulse)
# ALU output "ready" side. alu "ready" indication stays hi until
# ALU says "valid".
m.submodules.alu_l = alu_l = SRLatch(False, name="alu")
- m.d.comb += self.alu.n.ready_i.eq(alu_l.q)
- m.d.sync += alu_l.r.eq(self.alu.n.valid_o & alu_l.q)
- m.d.comb += alu_l.s.eq(all_rd_pulse)
+ m.d.comb += self.alu.n.i_ready.eq(alu_l.q)
+ m.d.sync += alu_l.r.eq(self.alu.n.o_valid & alu_l.q)
+ m.d.comb += alu_l.s.eq(all_rd_pulse) # XXX LOOP
# -----
# outputs
m.d.comb += self.busy_o.eq(opc_l.q) # busy out
# read-release gated by busy (and read-mask)
- bro = Repl(self.busy_o, self.n_src)
- m.d.comb += self.rd.rel.eq(src_l.q & bro & slg & ~self.rdmaskn)
+ if True: #self.sync_rw: - experiment (doesn't work)
+ bro = Repl(self.busy_o, self.n_src)
+ else:
+ bro = Repl(self.busy_o|self.issue_i, self.n_src)
+ m.d.comb += self.rd.rel_o.eq(src_l.q & bro & slg)
# write-release gated by busy and by shadow (and write-mask)
brd = Repl(self.busy_o & self.shadown_i, self.n_dst)
- m.d.comb += self.wr.rel.eq(req_l.q & brd & self.wrmask)
+ m.d.comb += self.wr.rel_o.eq(req_l.q_int & brd)
# output the data from the latch on go_write
for i in range(self.n_dst):
- with m.If(self.wr.go[i] & self.busy_o):
+ with m.If(self.wr.go_i[i] & self.busy_o):
m.d.comb += self.dest[i].eq(drl[i])
return m
return self.dest[i]
def __iter__(self):
- yield self.rd.go
- yield self.wr.go
+ yield self.rd.go_i
+ yield self.wr.go_i
yield self.issue_i
yield self.shadown_i
yield self.go_die_i
yield self.src1_i
yield self.src2_i
yield self.busy_o
- yield self.rd.rel
- yield self.wr.rel
- yield self.data_o
+ yield self.rd.rel_o
+ yield self.wr.rel_o
+ yield self.o_data
def ports(self):
return list(self)
projects / soc.git / blobdiff