rw_domain = m.d.sync
else:
rw_domain = m.d.comb
+ # generate a pulse on system reset, to reset any latches, if needed
+ system_reset = Signal(reset=1)
+ m.d.sync += system_reset.eq(0)
+
# add the ALU to the MultiCompUnit only if it is a "real" ALU
# see AllFunctionUnits as to why: a FunctionUnitBaseMulti
# only has one "real" ALU but multiple pseudo front-ends,
# ALU only proceeds when all src are ready. rd_rel_o is delayed
# so combine it with go_rd_i. if all bits are set we're good
all_rd = Signal(reset_less=True)
- m.d.comb += all_rd.eq(self.busy_o & rok_l.q &
+ m.d.comb += all_rd.eq(self.busy_o & # rok_l.q & # XXX LOOP
(((~self.rd.rel_o) | self.rd.go_i).all()))
# generate read-done pulse
all_rd_pulse = Signal(reset_less=True)
- m.d.comb += all_rd_pulse.eq(rising_edge(m, all_rd))
+ m.d.comb += all_rd_pulse.eq(rising_edge(m, all_rd)) # XXX LOOP
# create rising pulse from alu valid condition.
alu_done = self.cu.alu_done_o
m.d.comb += reset.eq(req_done | self.go_die_i)
m.d.comb += rst_r.eq(self.issue_i | self.go_die_i)
m.d.comb += reset_w.eq(self.wr.go_i | Repl(self.go_die_i, self.n_dst))
- m.d.comb += reset_r.eq(self.rd.go_i | Repl(self.go_die_i, self.n_src))
+ m.d.comb += reset_r.eq(self.rd.go_i | Repl(rst_r, self.n_src))
# read-done,wr-proceed latch
rw_domain += rok_l.s.eq(self.issue_i) # set up when issue starts
- rw_domain += rok_l.r.eq(self.alu.n.o_valid & self.busy_o) # ALU done
+ rw_domain += rok_l.r.eq(self.alu.n.o_valid & self.busy_o) # ALUdone LOOP
# wr-done, back-to-start latch
rw_domain += rst_l.s.eq(all_rd) # set when read-phase is fully done
m.d.sync += opc_l.s.eq(self.issue_i) # set on issue
m.d.sync += opc_l.r.eq(req_done) # reset on ALU
- # src operand latch (not using go_wr_i)
- m.d.sync += src_l.s.eq(Repl(self.issue_i, self.n_src) & ~self.rdmaskn)
+ # src operand latch (not using go_wr_i) ANDed with rdmask
+ rdmaskn = Signal(self.n_src)
+ latchregister(m, self.rdmaskn, rdmaskn, self.issue_i, name="rdmask_l")
+ m.d.sync += src_l.s.eq(Repl(self.issue_i, self.n_src) & ~rdmaskn)
m.d.sync += src_l.r.eq(reset_r)
# dest operand latch (not using issue_i)
rw_domain += req_l.s.eq(alu_pulsem & self.wrmask)
- m.d.sync += req_l.r.eq(reset_w | prev_wr_go)
+ m.d.comb += req_l.r.eq(reset_w | prev_wr_go |
+ Repl(system_reset, self.n_dst))
# pass operation to the ALU (sync: plenty time to wait for src reads)
op = self.get_op()
ok = Const(1, 1)
data_r_ok = Const(1, 1)
if isinstance(lro, Record):
+ print("wr fields", i, lro, lro.fields)
data_r = Record.like(lro, name=name)
- print("wr fields", i, lro, data_r.fields)
# bye-bye abstract interface design..
- fname = find_ok(data_r.fields)
+ fname = find_ok(lro.fields)
if fname:
ok = getattr(lro, fname)
data_r_ok = getattr(data_r, fname)
# XXX fails - wrok.append((ok|data_r_ok) & self.busy_o)
wrok.append(ok & self.busy_o)
else:
+ data_r = Signal.like(lro, name=name)
# really should retire this but it's part of unit tests
- data_r = Signal.like(lro, name=name, reset_less=True)
wrok.append(ok & self.busy_o)
- with m.If(alu_pulse):
- rw_domain += data_r.eq(lro)
+ #latchregister(m, lro, data_r, ok & self.busy_o, name=name)
+ latchregister(m, lro, data_r, alu_pulse, name=name)
with m.If(self.issue_i):
- rw_domain += data_r.eq(0)
+ m.d.comb += data_r.eq(0)
drl.append(data_r)
# ok, above we collated anything with an "ok" on the output side
m.submodules.alu_l = alu_l = SRLatch(False, name="alu")
m.d.comb += self.alu.n.i_ready.eq(alu_l.q)
m.d.sync += alu_l.r.eq(self.alu.n.o_valid & alu_l.q)
- m.d.comb += alu_l.s.eq(all_rd_pulse)
+ m.d.comb += alu_l.s.eq(all_rd_pulse) # XXX LOOP
# -----
# outputs
m.d.comb += self.busy_o.eq(opc_l.q) # busy out
# read-release gated by busy (and read-mask)
- bro = Repl(self.busy_o, self.n_src)
+ if True: #self.sync_rw: - experiment (doesn't work)
+ bro = Repl(self.busy_o, self.n_src)
+ else:
+ bro = Repl(self.busy_o|self.issue_i, self.n_src)
m.d.comb += self.rd.rel_o.eq(src_l.q & bro & slg)
# write-release gated by busy and by shadow (and write-mask)
brd = Repl(self.busy_o & self.shadown_i, self.n_dst)
- m.d.comb += self.wr.rel_o.eq(req_l.q & brd)
+ m.d.comb += self.wr.rel_o.eq(req_l.q_int & brd)
# output the data from the latch on go_write
for i in range(self.n_dst):
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