Reset req_l latch on system reset

[soc.git] / src / soc / experiment / compalu_multi.py

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index f76e40660ac3181bda5e4af48ef8aba97f952964..23ef36ea03077bef1b73e75c1d4b169b454ee99b 100644 (file)
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -182,6 +182,10 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
             rw_domain = m.d.sync
         else:
             rw_domain = m.d.comb
+        # generate a pulse on system reset, to reset any latches, if needed
+        system_reset = Signal(reset=1)
+        m.d.sync += system_reset.eq(0)
+
         # add the ALU to the MultiCompUnit only if it is a "real" ALU
         # see AllFunctionUnits as to why: a FunctionUnitBaseMulti
         # only has one "real" ALU but multiple pseudo front-ends,
@@ -198,12 +202,12 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         # ALU only proceeds when all src are ready.  rd_rel_o is delayed
         # so combine it with go_rd_i.  if all bits are set we're good
         all_rd = Signal(reset_less=True)
-        m.d.comb += all_rd.eq(self.busy_o & rok_l.q &
+        m.d.comb += all_rd.eq(self.busy_o & # rok_l.q & # XXX LOOP
                               (((~self.rd.rel_o) | self.rd.go_i).all()))
 
         # generate read-done pulse
         all_rd_pulse = Signal(reset_less=True)
-        m.d.comb += all_rd_pulse.eq(rising_edge(m, all_rd))
+        m.d.comb += all_rd_pulse.eq(rising_edge(m, all_rd)) # XXX LOOP
 
         # create rising pulse from alu valid condition.
         alu_done = self.cu.alu_done_o
@@ -241,11 +245,11 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         m.d.comb += reset.eq(req_done | self.go_die_i)
         m.d.comb += rst_r.eq(self.issue_i | self.go_die_i)
         m.d.comb += reset_w.eq(self.wr.go_i | Repl(self.go_die_i, self.n_dst))
-        m.d.comb += reset_r.eq(self.rd.go_i | Repl(self.go_die_i, self.n_src))
+        m.d.comb += reset_r.eq(self.rd.go_i | Repl(rst_r, self.n_src))
 
         # read-done,wr-proceed latch
         rw_domain += rok_l.s.eq(self.issue_i)  # set up when issue starts
-        rw_domain += rok_l.r.eq(self.alu.n.o_valid & self.busy_o)  # ALU done
+        rw_domain += rok_l.r.eq(self.alu.n.o_valid & self.busy_o) # ALUdone LOOP
 
         # wr-done, back-to-start latch
         rw_domain += rst_l.s.eq(all_rd)     # set when read-phase is fully done
@@ -258,12 +262,13 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         # src operand latch (not using go_wr_i) ANDed with rdmask
         rdmaskn = Signal(self.n_src)
         latchregister(m, self.rdmaskn, rdmaskn, self.issue_i, name="rdmask_l")
-        m.d.comb += src_l.s.eq(Repl(self.issue_i, self.n_src) & ~rdmaskn)
+        m.d.sync += src_l.s.eq(Repl(self.issue_i, self.n_src) & ~rdmaskn)
         m.d.sync += src_l.r.eq(reset_r)
 
         # dest operand latch (not using issue_i)
         rw_domain += req_l.s.eq(alu_pulsem & self.wrmask)
-        m.d.comb += req_l.r.eq(reset_w | prev_wr_go)
+        m.d.comb += req_l.r.eq(reset_w | prev_wr_go |
+                               Repl(system_reset, self.n_dst))
 
         # pass operation to the ALU (sync: plenty time to wait for src reads)
         op = self.get_op()
@@ -355,7 +360,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         m.submodules.alu_l = alu_l = SRLatch(False, name="alu")
         m.d.comb += self.alu.n.i_ready.eq(alu_l.q)
         m.d.sync += alu_l.r.eq(self.alu.n.o_valid & alu_l.q)
-        m.d.comb += alu_l.s.eq(all_rd_pulse)
+        m.d.comb += alu_l.s.eq(all_rd_pulse) # XXX LOOP
 
         # -----
         # outputs