reduce dcache/icache number of ways, to fit into ECP5 45k resource

[soc.git] / src / soc / experiment / dcache.py

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 04c222faefea4d19d21386602fe135d7fc5e4c91..39578ebc98dd5e6f9bbe1548a62d4634cdb2ed63 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -513,12 +513,14 @@ class DTLBUpdate(Elaboratable):
         print ("    TLB_NUM_WAYS", cfg.TLB_NUM_WAYS)
 
         # TAG and PTE Memory SRAMs. transparent, write-enables are TLB_NUM_WAYS
-        tagway = Memory(depth=cfg.TLB_SET_SIZE, width=cfg.TLB_TAG_WAY_BITS)
+        tagway = Memory(depth=cfg.TLB_SET_SIZE, width=cfg.TLB_TAG_WAY_BITS,
+                             attrs={'syn_ramstyle': "block_ram"})
         m.submodules.rd_tagway = rd_tagway = tagway.read_port()
         m.submodules.wr_tagway = wr_tagway = tagway.write_port(
                                     granularity=cfg.TLB_EA_TAG_BITS)
 
-        pteway = Memory(depth=cfg.TLB_SET_SIZE, width=cfg.TLB_PTE_WAY_BITS)
+        pteway = Memory(depth=cfg.TLB_SET_SIZE, width=cfg.TLB_PTE_WAY_BITS,
+                             attrs={'syn_ramstyle': "block_ram"})
         m.submodules.rd_pteway = rd_pteway = pteway.read_port()
         m.submodules.wr_pteway = wr_pteway = pteway.write_port(
                                     granularity=cfg.TLB_PTE_BITS)
@@ -745,10 +747,10 @@ class DCache(Elaboratable, DCacheConfig):
 
         if self.microwatt_compat:
             # reduce way sizes and num lines
-            super().__init__(NUM_LINES = 16,
+            super().__init__(NUM_LINES = 2,
                               NUM_WAYS = 1,
                               TLB_NUM_WAYS = 1,
-                              TLB_SET_SIZE=16) # XXX needs device-tree entry
+                              TLB_SET_SIZE=2) # XXX needs device-tree entry
         else:
             super().__init__()
 
@@ -845,7 +847,7 @@ class DCache(Elaboratable, DCacheConfig):
             return
 
         # suite of PLRUs with a selection and output mechanism
-        tlb_plrus = PLRUs(self.TLB_SET_SIZE, self.TLB_WAY_BITS)
+        tlb_plrus = PLRUs("d_tlb", self.TLB_SET_SIZE, self.TLB_WAY_BITS)
         m.submodules.tlb_plrus = tlb_plrus
         comb += tlb_plrus.way.eq(r1.tlb_hit.way)
         comb += tlb_plrus.valid.eq(r1.tlb_hit.valid)
@@ -951,7 +953,8 @@ class DCache(Elaboratable, DCacheConfig):
             return
 
         # suite of PLRUs with a selection and output mechanism
-        m.submodules.plrus = plrus = PLRUs(self.NUM_LINES, self.WAY_BITS)
+        m.submodules.plrus = plrus = PLRUs("dtag", self.NUM_LINES,
+                                                   self.WAY_BITS)
         comb += plrus.way.eq(r1.hit_way)
         comb += plrus.valid.eq(r1.cache_hit)
         comb += plrus.index.eq(r1.hit_index)
@@ -966,8 +969,9 @@ class DCache(Elaboratable, DCacheConfig):
 
         m_in, d_in = self.m_in, self.d_in
 
-        # synchronous tag read-port
-        m.submodules.rd_tag = rd_tag = self.tagmem.read_port()
+        # synchronous tag read-port: NOT TRANSPARENT (cannot pass through
+        # write-to-a-read at the same time), seems to pass tests ok
+        m.submodules.rd_tag = rd_tag = self.tagmem.read_port(transparent=False)
 
         index = Signal(self.INDEX_BITS)
 
@@ -1586,20 +1590,14 @@ class DCache(Elaboratable, DCacheConfig):
                         pass
 
             with m.Case(State.RELOAD_WAIT_ACK):
-                ld_stbs_done = Signal()
-                # Requests are all sent if stb is 0
-                comb += ld_stbs_done.eq(~r1.wb.stb)
 
                 # If we are still sending requests, was one accepted?
                 with m.If((~bus.stall) & r1.wb.stb):
-                    # That was the last word?  We are done sending.
-                    # Clear stb and set ld_stbs_done so we can handle an
-                    # eventual last ack on the same cycle.
+                    # That was the last word?  We are done sending.  Clear stb 
                     # sigh - reconstruct wb adr with 3 extra 0s at front
                     wb_adr = Cat(Const(0, self.ROW_OFF_BITS), r1.wb.adr)
                     with m.If(self.is_last_row_addr(wb_adr, r1.end_row_ix)):
                         sync += r1.wb.stb.eq(0)
-                        comb += ld_stbs_done.eq(1)
 
                     # Calculate the next row address in the current cache line
                     rlen = self.LINE_OFF_BITS-self.ROW_OFF_BITS
@@ -1638,7 +1636,7 @@ class DCache(Elaboratable, DCacheConfig):
                         sync += r1.use_forward1.eq(1)
 
                     # Check for completion
-                    with m.If(ld_stbs_done & lastrow):
+                    with m.If(lastrow):
                         # Complete wishbone cycle
                         sync += r1.wb.cyc.eq(0)
 
@@ -1757,7 +1755,8 @@ class DCache(Elaboratable, DCacheConfig):
         cache_valids     = self.CacheValidsArray()
         cache_tag_set    = Signal(self.TAG_RAM_WIDTH)
 
-        self.tagmem = Memory(depth=self.NUM_LINES, width=self.TAG_RAM_WIDTH)
+        self.tagmem = Memory(depth=self.NUM_LINES, width=self.TAG_RAM_WIDTH,
+                             attrs={'syn_ramstyle': "block_ram"})
 
         """note: these are passed to nmigen.hdl.Memory as "attributes".
            don't know how, just that they are.