reduce dcache/icache number of ways, to fit into ECP5 45k resource

[soc.git] / src / soc / experiment / dcache.py

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 917e9818999538375ac3ef0e88b4b911687f69c1..39578ebc98dd5e6f9bbe1548a62d4634cdb2ed63 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -747,10 +747,10 @@ class DCache(Elaboratable, DCacheConfig):
 
         if self.microwatt_compat:
             # reduce way sizes and num lines
-            super().__init__(NUM_LINES = 4,
+            super().__init__(NUM_LINES = 2,
                               NUM_WAYS = 1,
                               TLB_NUM_WAYS = 1,
-                              TLB_SET_SIZE=4) # XXX needs device-tree entry
+                              TLB_SET_SIZE=2) # XXX needs device-tree entry
         else:
             super().__init__()
 
@@ -847,7 +847,7 @@ class DCache(Elaboratable, DCacheConfig):
             return
 
         # suite of PLRUs with a selection and output mechanism
-        tlb_plrus = PLRUs(self.TLB_SET_SIZE, self.TLB_WAY_BITS)
+        tlb_plrus = PLRUs("d_tlb", self.TLB_SET_SIZE, self.TLB_WAY_BITS)
         m.submodules.tlb_plrus = tlb_plrus
         comb += tlb_plrus.way.eq(r1.tlb_hit.way)
         comb += tlb_plrus.valid.eq(r1.tlb_hit.valid)
@@ -953,7 +953,8 @@ class DCache(Elaboratable, DCacheConfig):
             return
 
         # suite of PLRUs with a selection and output mechanism
-        m.submodules.plrus = plrus = PLRUs(self.NUM_LINES, self.WAY_BITS)
+        m.submodules.plrus = plrus = PLRUs("dtag", self.NUM_LINES,
+                                                   self.WAY_BITS)
         comb += plrus.way.eq(r1.hit_way)
         comb += plrus.valid.eq(r1.cache_hit)
         comb += plrus.index.eq(r1.hit_index)