Add count of masked reads

[soc.git] / src / soc / experiment / formal / proof_compalu_multi.py

diff --git a/src/soc/experiment/formal/proof_compalu_multi.py b/src/soc/experiment/formal/proof_compalu_multi.py
index 07ff40026659337c291c44414b04e1d9249971ba..4e15462b5d3c9c0f7df8fe8f411021e38268ad8e 100644 (file)
--- a/src/soc/experiment/formal/proof_compalu_multi.py
+++ b/src/soc/experiment/formal/proof_compalu_multi.py
@@ -115,17 +115,42 @@ class CompALUMultiTestCase(FHDLTestCase):
         m.d.sync += cnt_issue.eq(cnt_issue + do_issue)
         do_read = Signal(dut.n_src)
         m.d.comb += do_read.eq(dut.cu.rd.rel_o & dut.cu.rd.go_i)
-        m.d.sync += cnt_issue.eq(cnt_issue + do_issue)
         cnt_read = []
         for i in range(dut.n_src):
             cnt = Signal(4, name="cnt_read_%d" % i)
             m.d.sync += cnt.eq(cnt + do_read[i])
             cnt_read.append(cnt)
+        do_write = Signal(dut.n_dst)
+        m.d.comb += do_write.eq(dut.cu.wr.rel_o & dut.cu.wr.go_i)
+        cnt_write = []
+        for i in range(dut.n_dst):
+            cnt = Signal(4, name="cnt_write_%d" % i)
+            m.d.sync += cnt.eq(cnt + do_write[i])
+            cnt_write.append(cnt)
+        do_alu_write = Signal()
+        m.d.comb += do_alu_write.eq(alu.p.i_valid & alu.p.o_ready)
+        cnt_alu_write = Signal(4)
+        m.d.sync += cnt_alu_write.eq(cnt_alu_write + do_alu_write)
+        do_alu_read = Signal()
+        m.d.comb += do_alu_read.eq(alu.n.o_valid & alu.n.i_ready)
+        cnt_alu_read = Signal(4)
+        m.d.sync += cnt_alu_read.eq(cnt_alu_read + do_alu_read)
+        cnt_masked_read = []
+        for i in range(dut.n_src):
+            cnt = Signal(4, name="cnt_masked_read_%d" % i)
+            m.d.sync += cnt.eq(cnt + (do_issue & dut.rdmaskn[i]))
+            cnt_masked_read.append(cnt)
 
         # Ask the formal engine to give an example
         m.d.comb += Cover((cnt_issue == 2)
                           & (cnt_read[0] == 1)
-                          & (cnt_read[1] == 0))
+                          & (cnt_read[1] == 1)
+                          & (cnt_write[0] == 1)
+                          & (cnt_write[1] == 1)
+                          & (cnt_alu_write == 1)
+                          & (cnt_alu_read == 1)
+                          & (cnt_masked_read[0] == 1)
+                          & (cnt_masked_read[1] == 1))
         self.assertFormal(m, mode="cover", depth=10)