If the ALU is idle, do not assert valid

[soc.git] / src / soc / experiment / formal / proof_compalu_multi.py

diff --git a/src/soc/experiment/formal/proof_compalu_multi.py b/src/soc/experiment/formal/proof_compalu_multi.py
index d81f35e12151518a77a2bf5358016acef9c7952c..6edb8043b564323d339ae82d638df2cb2bd66fd1 100644 (file)
--- a/src/soc/experiment/formal/proof_compalu_multi.py
+++ b/src/soc/experiment/formal/proof_compalu_multi.py
@@ -35,7 +35,7 @@ https://bugs.libre-soc.org/show_bug.cgi?id=197
 import unittest
 
 from nmigen import Signal, Module
-from nmigen.hdl.ast import Cover
+from nmigen.hdl.ast import Cover, Const, Assume
 from nmutil.formaltest import FHDLTestCase
 from nmutil.singlepipe import ControlBase
 
@@ -141,8 +141,17 @@ class CompALUMultiTestCase(FHDLTestCase):
         cnt_masked_read = []
         for i in range(dut.n_src):
             cnt = Signal(4, name="cnt_masked_read_%d" % i)
-            m.d.sync += cnt.eq(cnt + (do_issue & dut.rdmaskn[i]))
+            if i == 0:
+                extra = dut.oper_i.zero_a
+            elif i == 1:
+                extra = dut.oper_i.imm_data.ok
+            else:
+                extra = Const(0, 1)
+            m.d.sync += cnt.eq(cnt + (do_issue & (dut.rdmaskn[i] | extra)))
             cnt_masked_read.append(cnt)
+        # If the ALU is idle, do not assert valid
+        with m.If(cnt_alu_read == cnt_alu_write):
+            m.d.comb += Assume(~alu.n.o_valid)
 
         # Ask the formal engine to give an example
         m.d.comb += Cover((cnt_issue == 2)