add fabric compatibility mode

[soc.git] / src / soc / experiment / icache.py

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 02b54a03932f56d151b6c553950b3d4385341d15..064f39b629e2388616a47be04726cd1c290b1853 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -335,22 +335,36 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig):
         # use FetchUnitInterface, helps keep some unit tests running
         self.use_fetch_iface = False
 
-        # test if microwatt compatibility is to be enabled
+        # test if small cache to be enabled
+        self.small_cache = (hasattr(pspec, "small_cache") and
+                                 (pspec.small_cache == True))
+        # test if microwatt compatibility to be enabled
         self.microwatt_compat = (hasattr(pspec, "microwatt_compat") and
                                  (pspec.microwatt_compat == True))
+        # test if fabric compatibility is to be enabled
+        self.fabric_compat = (hasattr(pspec, "fabric_compat") and
+                                 (pspec.fabric_compat == True))
 
         XLEN = pspec.XLEN
-
-        if self.microwatt_compat:
-            # reduce way sizes and num lines
-            ICacheConfig.__init__(self, LINE_SIZE=XLEN,
-                                        XLEN=XLEN,
-                                        NUM_LINES = 4,
-                                        NUM_WAYS = 1,
-                                        TLB_SIZE=4 # needs device-tree update
-                                 )
-        else:
-            ICacheConfig.__init__(self, LINE_SIZE=XLEN, XLEN=XLEN)
+        LINE_SIZE = 64
+        TLB_SIZE = 8
+        NUM_LINES = 8
+        NUM_WAYS = 2
+        if self.small_cache:
+            # reduce way sizes and num lines to ridiculously small
+            NUM_LINES = 2
+            NUM_WAYS = 1
+            TLB_SIZE = 2
+        if self.microwatt_compat or self.fabric_compat:
+            # reduce way sizes
+            NUM_WAYS = 1
+
+        ICacheConfig.__init__(self, LINE_SIZE=LINE_SIZE,
+                                    XLEN=XLEN,
+                                    NUM_LINES = NUM_LINES,
+                                    NUM_WAYS = NUM_WAYS,
+                                    TLB_SIZE=TLB_SIZE
+                             )
 
     def use_fetch_interface(self):
         self.use_fetch_iface = True
@@ -419,7 +433,8 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig):
             return
 
 
-        m.submodules.plrus = plru = PLRUs(self.NUM_LINES, self.WAY_BITS)
+        m.submodules.plrus = plru = PLRUs("itag", self.NUM_LINES,
+                                                  self.WAY_BITS)
         comb += plru.way.eq(r.hit_way)
         comb += plru.valid.eq(r.hit_valid)
         comb += plru.index.eq(self.get_index(r.hit_nia))
@@ -704,7 +719,7 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig):
         # If we are still sending requests, was one accepted?
         with m.If(~bus.stall & r.wb.stb):
             # That was the last word? We are done sending.  Clear stb
-            with m.If(self.is_last_row_addr(r.wb.adr, r.end_row_ix)):
+            with m.If(self.is_last_row_addr(r.req_adr, r.end_row_ix)):
                 sync += Display("IS_LAST_ROW_ADDR r.wb.addr:%x "
                          "r.end_row_ix:%x r.wb.stb:%x",
                          r.wb.adr, r.end_row_ix, r.wb.stb)