reduce dcache/icache number of ways, to fit into ECP5 45k resource

[soc.git] / src / soc / experiment / icache.py

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 5523c50ca0fd3b1e0b7a7dcf5d30978db4fd77fe..b0b674c845601d369d379e880f199ef563df4263 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -345,9 +345,9 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig):
             # reduce way sizes and num lines
             ICacheConfig.__init__(self, LINE_SIZE=XLEN,
                                         XLEN=XLEN,
-                                        NUM_LINES = 4,
+                                        NUM_LINES = 2,
                                         NUM_WAYS = 1,
-                                        TLB_SIZE=4 # needs device-tree update
+                                        TLB_SIZE=2 # needs device-tree update
                                  )
         else:
             ICacheConfig.__init__(self, LINE_SIZE=XLEN, XLEN=XLEN)
@@ -419,7 +419,8 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig):
             return
 
 
-        m.submodules.plrus = plru = PLRUs(self.NUM_LINES, self.WAY_BITS)
+        m.submodules.plrus = plru = PLRUs("itag", self.NUM_LINES,
+                                                  self.WAY_BITS)
         comb += plru.way.eq(r.hit_way)
         comb += plru.valid.eq(r.hit_valid)
         comb += plru.index.eq(self.get_index(r.hit_nia))