from soc.fu.cr.cr_input_record import CompCROpSubset
from soc.experiment.alu_hier import ALU, DummyALU
from soc.experiment.compalu_multi import MultiCompUnit
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
from nmutil.gtkw import write_gtkw
from nmigen import Module, Signal
from nmigen.cli import rtlil
# transaction parameters, passed via signals
self.delay = Signal(8)
self.data = Signal.like(self.port)
+ self.data_valid = False
# add ourselves to the simulation process list
sim.add_sync_process(self._process)
yield
yield Settle()
# read the transaction parameters
+ assert self.data_valid, "an unexpected operand was consumed"
delay = (yield self.delay)
data = (yield self.data)
# wait for `delay` cycles
yield self.port.eq(data)
yield self.count.eq(self.count + 1)
yield
+ self.data_valid = False
yield self.go_i.eq(0)
yield self.port.eq(0)
"""
yield self.data.eq(data)
yield self.delay.eq(delay)
+ self.data_valid = True
class ResultConsumer:
# transaction parameters, passed via signals
self.delay = Signal(8)
self.expected = Signal.like(self.port)
+ self.expecting = False
# add ourselves to the simulation process list
sim.add_sync_process(self._process)
yield
yield Settle()
# read the transaction parameters
+ assert self.expecting, "an unexpected result was produced"
delay = (yield self.delay)
expected = (yield self.expected)
# wait for `delay` cycles
"""
yield self.expected.eq(expected)
yield self.delay.eq(delay)
+ self.expecting = True
def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
self.consumers.append(ResultConsumer(sim, dut, i))
def issue(self, src_i, op, expected, src_delays, dest_delays,
- inv_a=0, imm=0, imm_ok=0, zero_a=0,
+ inv_a=0, imm=0, imm_ok=0, zero_a=0, rc=0,
rdmaskn=None, wrmask=None):
"""Executes the issue operation"""
dut = self.dut
yield dut.oper_i.imm_data.ok.eq(imm_ok)
if hasattr(dut.oper_i, "zero_a"):
yield dut.oper_i.zero_a.eq(zero_a)
+ if hasattr(dut.oper_i, "rc"):
+ yield dut.oper_i.rc.rc.eq(rc)
if hasattr(dut, "rdmaskn"):
rdmaskn_bits = 0
for i in range(len(rdmaskn)):
yield self.dut.oper_i.imm_data.ok.eq(0)
if hasattr(dut.oper_i, "zero_a"):
yield self.dut.oper_i.zero_a.eq(0)
+ if hasattr(dut.oper_i, "rc"):
+ yield dut.oper_i.rc.rc.eq(0)
# wait for busy to be negated
yield Settle()
while (yield dut.busy_o):
def scoreboard_sim(op):
+ # the following tests cases have rc=0, so no CR output is expected
# zero (no) input operands test
# 0 + 8 = 8
- yield from op.issue([5, 2], MicrOp.OP_ADD, [8],
+ yield from op.issue([5, 2], MicrOp.OP_ADD, [8, 0],
zero_a=1, imm=8, imm_ok=1,
- src_delays=[0, 2], dest_delays=[0])
+ wrmask=[0, 1],
+ src_delays=[0, 2], dest_delays=[0, 0])
# 5 + 8 = 13
- yield from op.issue([5, 2], MicrOp.OP_ADD, [13],
+ yield from op.issue([5, 2], MicrOp.OP_ADD, [13, 0],
inv_a=0, imm=8, imm_ok=1,
- src_delays=[2, 0], dest_delays=[2])
+ wrmask=[0, 1],
+ src_delays=[2, 0], dest_delays=[2, 0])
# 5 + 2 = 7
- yield from op.issue([5, 2], MicrOp.OP_ADD, [7],
- src_delays=[1, 1], dest_delays=[1])
+ yield from op.issue([5, 2], MicrOp.OP_ADD, [7, 0],
+ wrmask=[0, 1],
+ src_delays=[1, 1], dest_delays=[1, 0])
# (-6) + 2 = (-4)
- yield from op.issue([5, 2], MicrOp.OP_ADD, [65532],
+ yield from op.issue([5, 2], MicrOp.OP_ADD, [65532, 0],
inv_a=1,
- src_delays=[1, 2], dest_delays=[0])
+ wrmask=[0, 1],
+ src_delays=[1, 2], dest_delays=[0, 0])
# 0 + 2 = 2
- yield from op.issue([5, 2], MicrOp.OP_ADD, [2],
+ yield from op.issue([5, 2], MicrOp.OP_ADD, [2, 0],
zero_a=1,
- src_delays=[2, 0], dest_delays=[1])
+ wrmask=[0, 1],
+ src_delays=[2, 0], dest_delays=[1, 0])
+
+ # test all combinations of masked input ports
+ # NOP does not make any request nor response
+ yield from op.issue([5, 2], MicrOp.OP_NOP, [0, 0],
+ rdmaskn=[1, 1], wrmask=[1, 1],
+ src_delays=[1, 2], dest_delays=[1, 0])
+ # sign_extend(0x80) = 0xFF80
+ yield from op.issue([0x80, 2], MicrOp.OP_EXTS, [0xFF80, 0],
+ rdmaskn=[0, 1], wrmask=[0, 1],
+ src_delays=[2, 1], dest_delays=[0, 0])
+ # sign_extend(0x80) = 0xFF80
+ yield from op.issue([2, 0x80], MicrOp.OP_EXTSWSLI, [0xFF80, 0],
+ rdmaskn=[1, 0], wrmask=[0, 1],
+ src_delays=[1, 2], dest_delays=[1, 0])
# test combinatorial zero-delay operation
# In the test ALU, any operation other than ADD, MUL, EXTS or SHR
# is zero-delay, and do a subtraction.
# 5 - 2 = 3
- yield from op.issue([5, 2], MicrOp.OP_NOP, [3],
- src_delays=[0, 1], dest_delays=[2])
- # test all combinations of masked input ports
+ yield from op.issue([5, 2], MicrOp.OP_CMP, [3, 0],
+ wrmask=[0, 1],
+ src_delays=[0, 1], dest_delays=[2, 0])
+
+ # test with rc=1, so expect results on the CR output port
+ # 5 + 2 = 7
+ # 7 > 0 => CR = 0b100
+ yield from op.issue([5, 2], MicrOp.OP_ADD, [7, 0b100],
+ rc=1,
+ src_delays=[1, 1], dest_delays=[1, 0])
# sign_extend(0x80) = 0xFF80
- yield from op.issue([0x80, 2], MicrOp.OP_EXTS, [0xFF80],
- rdmaskn=[0, 1],
- src_delays=[2, 1], dest_delays=[0])
- # 0 (masked) + 2 = 2
- yield from op.issue([5, 2], MicrOp.OP_ADD, [2],
- rdmaskn=[1, 0],
- src_delays=[1, 2], dest_delays=[1])
- # 0 (masked) + 0 (masked) = 0
- yield from op.issue([5, 2], MicrOp.OP_ADD, [0],
- rdmaskn=[1, 1],
- src_delays=[1, 2], dest_delays=[1])
- # note: the current test ALU down not have any masked write operations
+ # -128 < 0 => CR = 0b010
+ yield from op.issue([0x80, 2], MicrOp.OP_EXTS, [0xFF80, 0b010],
+ rc=1, rdmaskn=[0, 1],
+ src_delays=[2, 1], dest_delays=[0, 2])
+ # 5 - 5 = 0
+ # 0 == 0 => CR = 0b001
+ yield from op.issue([5, 2], MicrOp.OP_CMP, [0, 0b001],
+ imm=5, imm_ok=1, rc=1,
+ src_delays=[0, 1], dest_delays=[2, 1])
def test_compunit_fsm():
('prev port', 'in', [
'op__sdir', 'p_data_i[7:0]', 'p_shift_i[7:0]',
({'submodule': 'p'},
- ['p_valid_i', 'p_ready_o'])]),
+ ['p_i_valid', 'p_o_ready'])]),
('next port', 'out', [
'n_data_o[7:0]',
({'submodule': 'n'},
- ['n_valid_o', 'n_ready_i'])])]),
- ('debug', {'module': 'top'},
+ ['n_o_valid', 'n_i_ready'])])]),
+ ('debug', {'module': 'bench'},
['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]
write_gtkw(
"test_compunit_fsm1.gtkw",
"test_compunit_fsm1.vcd",
traces, style,
- module='top.cu'
+ module='bench.top.cu'
)
m = Module()
alu = Shifter(8)
m = Module()
alu = ALU(16)
- dut = MultiCompUnit(16, alu, CompALUOpSubset)
+ dut = MultiCompUnit(16, alu, CompALUOpSubset, n_dst=2)
m.submodules.cu = dut
vl = rtlil.convert(dut, ports=dut.ports())
('alu', {'submodule': 'alu'}, [
('prev port', 'in', [
'oper_i_None__insn_type', 'i1[15:0]',
- 'valid_i', 'ready_o']),
+ 'i_valid', 'o_ready']),
('next port', 'out', [
- 'alu_o[15:0]', 'valid_o', 'ready_i'])])]
+ 'alu_o[15:0]', 'o_valid', 'i_ready'])])]
write_gtkw("test_compunit_regspec3.gtkw",
"test_compunit_regspec3.vcd",
traces, style,
clk_period=1e-6,
- module='top.cu')
+ module='bench.top.cu')
inspec = [('INT', 'a', '0:15'),
('INT', 'b', '0:15'),
('oper_i_None__invert_in', {'display': 'invert_in'}),
('oper_i_None__imm_data__data[63:0]', {'display': 'data[63:0]'}),
('oper_i_None__imm_data__ok', {'display': 'imm_ok'}),
- ('oper_i_None__zero_a', {'display': 'zero_a'})]),
+ ('oper_i_None__zero_a', {'display': 'zero_a'}),
+ ('oper_i_None__rc__rc', {'display': 'rc'})]),
('operand 1 port', 'in', [
('cu_rdmaskn_i[1:0]', {'bit': 1}),
('cu_rd__rel_o[1:0]', {'bit': 1}),
('cu_rd__go_i[1:0]', {'bit': 0}),
'src2_i[15:0]']),
('result port', 'out', [
- 'cu_wrmask_o', 'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']),
+ ('cu_wrmask_o[1:0]', {'bit': 1}),
+ ('cu_wr__rel_o[1:0]', {'bit': 1}),
+ ('cu_wr__go_i[1:0]', {'bit': 1}),
+ 'dest1_o[15:0]']),
+ ('cr port', 'out', [
+ ('cu_wrmask_o[1:0]', {'bit': 0}),
+ ('cu_wr__rel_o[1:0]', {'bit': 0}),
+ ('cu_wr__go_i[1:0]', {'bit': 0}),
+ 'dest2_o[15:0]']),
('alu', {'submodule': 'alu'}, [
('prev port', 'in', [
'op__insn_type', 'op__invert_in', 'a[15:0]', 'b[15:0]',
- 'valid_i', 'ready_o']),
+ 'i_valid', 'o_ready']),
('next port', 'out', [
- 'alu_o[15:0]', 'valid_o', 'ready_i'])]),
- ('debug', {'module': 'top'},
+ 'alu_o[15:0]', 'o_valid', 'i_ready',
+ 'alu_o_ok', 'alu_cr_ok'])]),
+ ('debug', {'module': 'bench'},
['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]
write_gtkw("test_compunit_regspec1.gtkw",
"test_compunit_regspec1.vcd",
traces, style,
clk_period=1e-6,
- module='top.cu')
+ module='bench.top.cu')
inspec = [('INT', 'a', '0:15'),
('INT', 'b', '0:15')]
- outspec = [('INT', 'o', '0:15')]
+ outspec = [('INT', 'o', '0:15'),
+ ('INT', 'cr', '0:15')]
regspec = (inspec, outspec)
projects / soc.git / blobdiff