format code

[soc.git] / src / soc / fu / alu / formal / proof_input_stage.py

diff --git a/src/soc/fu/alu/formal/proof_input_stage.py b/src/soc/fu/alu/formal/proof_input_stage.py
index 107be930091e65d45dc984a5c4f26903e4ce7a98..001c063e0a1ec05a939162b6bab5aa1702dec0ec 100644 (file)
--- a/src/soc/fu/alu/formal/proof_input_stage.py
+++ b/src/soc/fu/alu/formal/proof_input_stage.py
@@ -66,6 +66,7 @@ class GTCombinerTestCase(FHDLTestCase):
         module = Driver()
         self.assertFormal(module, mode="bmc", depth=4)
         self.assertFormal(module, mode="cover", depth=4)
+
     def test_ilang(self):
         dut = Driver()
         vl = rtlil.convert(dut, ports=[])