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add parent_pspec everywhere
[soc.git]
/
src
/
soc
/
fu
/
alu
/
formal
/
proof_input_stage.py
diff --git
a/src/soc/fu/alu/formal/proof_input_stage.py
b/src/soc/fu/alu/formal/proof_input_stage.py
index 001c063e0a1ec05a939162b6bab5aa1702dec0ec..ba65373b646dcdde5a90e89161aae7bdea65a578 100644
(file)
--- a/
src/soc/fu/alu/formal/proof_input_stage.py
+++ b/
src/soc/fu/alu/formal/proof_input_stage.py
@@
-32,7
+32,7
@@
class Driver(Elaboratable):
recwidth += width
comb += p.eq(AnyConst(width))
- pspec = ALUPipeSpec(id_wid=2, op_wid=recwidth)
+ pspec = ALUPipeSpec(id_wid=2, op_wid=recwidth
, parent_pspec=None
)
m.submodules.dut = dut = ALUInputStage(pspec)
a = Signal(64)